gpm module and exec first buggy version.

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 095d4dc5e813bc1a00a3be9882ca5d49261199cc..080fb00accba7186704cd9e474927f4c8c5a4beb 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -12,28 +12,41 @@ signal op_group : op_info_t;
 signal op_detail : op_opt_t;
 signal left_operand, right_operand : gp_register_t;
 signal alu_state, alu_nxt : alu_result_rec;
-
 signal psw : status_rec;
 
+type exec_internal is record
+        result : gp_register_t;
+        res_addr : gp_addr_t;
+        alu_jump : std_logic;
+        brpr    : std_logic;
+        wr_en   : std_logic;
+end record;
+
+signal reg, reg_nxt : exec_internal;
+
 begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt);
+        op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
 
-syn: process(sys_clk, reset)
+syn: process(clk, reset)
 
 begin
 
-       if (reset = RESET_VALUE) then
-               condition <=                    
-       elsif rising_edge(sys_clk) then
-               
+       if reset = RESET_VALUE then
+               reg.alu_jmp <= '0';
+                reg.brpr <= '0';
+                reg.wr_en <= '0';
+                reg.result <= (others =>'0');
+                reg.res_addr <= (others => '0');                       
+       elsif rising_edge(clk) then
+               reg <= reg_nxt;
        end if;
        
 end process;
 
-asyn: process(reset,condition)
+asyn: process(reset,dec_instr, alu_nxt, psw)
 begin
 
         condition <= dec_instr.condition;
@@ -42,20 +55,33 @@ begin
         left_operand <= dec_instr.src1;
         right_operand <= dec_instr.src2;
 
-        alu_state.status <= psw;
-        alu_state.result_addr <= dec_instr.daddr;
-        alu_state.brpr <= brpr;
-        alu_state.reg_op <= '0';
-        alu_state.mem_op <= '0';
-        alu_state.
+
+        alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
+        
 
         if reset = RESET_VALUE then
                 condition <= COND_NEVER;
         else
                 
         end if;
+        
+        reg_nxt.brpr <= alu_nxt.brpr;
+        reg_nxt.alu_jump <= alu_nxt.alu_jump;
+        reg_nxt.wr_en <= alu_nxt.reg_op;
+        reg_nxt.result <= alu_nxt.result;
+        reg_nxt.reg_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
+result <= reg.result;
+result_addr <= reg.res_addr;
+alu_jmp <= reg.alu_jump;
+brbr <= reg.brpr;
+wr_en <= reg.wr_en;
+dmem <= alu_nxt.mem_op;
+dmem_write_en <= alu_nxt.mem_en;
+hword <= alu_nxt.hw_op;
+byte_s <= alu_nxt.byte_op;
+
 end behav;