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added pipe 2 reg, testbench, top_level_entity, ...
[calu.git]
/
cpu
/
src
/
exec_op
/
shift_op_b.vhd
diff --git
a/cpu/src/exec_op/shift_op_b.vhd
b/cpu/src/exec_op/shift_op_b.vhd
old mode 100755
(executable)
new mode 100644
(file)
index
0b5a73c
..
f0acce6
--- a/
cpu/src/exec_op/shift_op_b.vhd
+++ b/
cpu/src/exec_op/shift_op_b.vhd
@@
-11,8
+11,8
@@
architecture shift_op of exec_op is
begin
- logic <= op_detail(
LOG
_OPT);
- ls <= op_detail(
LEF
T_OPT);
+ logic <= op_detail(
ARITH
_OPT);
+ ls <= op_detail(
RIGH
T_OPT);
carry <= op_detail(CARRY_OPT);
calc: process(left_operand, right_operand, logic,ls, carry, alu_state)