Fixed some bugs.
[calu.git] / cpu / src / exec_op / shift_op_b.vhd
index 7f00dcfb6a4d2b74e5b440d9c85ca77b9d2cc1b6..6e17280c833aed0a1619e81dd44727e79528a26c 100644 (file)
@@ -7,17 +7,12 @@ use work.alu_pkg.all;
 
 architecture shift_op of exec_op is
 
-       signal logic, ls, carry : std_logic;
+       signal arith, rs, carry : std_logic;
 
 begin
 
-<<<<<<< HEAD
        arith <=  op_detail(ARITH_OPT);
        rs      <=  op_detail(RIGHT_OPT);
-=======
-       logic <=  op_detail(ARITH_OPT);
-       ls      <=  op_detail(RIGHT_OPT);
->>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff
        carry <= op_detail(CARRY_OPT);
 
 calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
@@ -30,13 +25,13 @@ begin
                 if rs = '1' then   
                        tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
                        tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
                else 
                        tmp_sb := (carry and alu_state.status.carry and not(arith));
                        tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
                end if;