pipe2

[calu.git] / cpu / src / exec_op / shift_op_b.vhd

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
index 291b5902de21c62dce10663a71cbbf624fcaf485..0b5a73cb80bc72677b6bb8dedb511f0b2d509d31 100755 (executable)
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -1,46 +1,46 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture shift_op of exec_op is\r
-\r
-       signal logic, ls, carry : std_logic;\r
-\r
-begin\r
-\r
-       logic <=  op_detail(LOG_OPT);\r
-       ls      <=  op_detail(LEFT_OPT);\r
-       carry <= op_detail(CARRY_OPT);\r
-\r
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)\r
-               variable alu_result_v : alu_result_rec;\r
-               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
-               variable tmp_sb : std_logic;\r
-       begin\r
-               alu_result_v := alu_state;\r
-               \r
-               if ls = '1' then\r
-                       tmp_sb := (carry and alu_state.status.carry and logic);\r
-                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);\r
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
-                       \r
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);\r
-                       \r
-               else\r
-                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));\r
-                       tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);\r
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
-                       \r
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);\r
-               end if;\r
-               \r
-               alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);\r
-               \r
-               alu_result <= alu_result_v;\r
-               \r
-end process;\r
-\r
-end architecture shift_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture shift_op of exec_op is
+
+       signal logic, ls, carry : std_logic;
+
+begin
+
+       logic <=  op_detail(LOG_OPT);
+       ls      <=  op_detail(LEFT_OPT);
+       carry <= op_detail(CARRY_OPT);
+
+calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+               variable alu_result_v : alu_result_rec;
+               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
+               variable tmp_sb : std_logic;
+       begin
+               alu_result_v := alu_state;
+               
+               if ls = '1' then
+                       tmp_sb := (carry and alu_state.status.carry and logic);
+                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
+                       
+               else
+                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
+                       tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
+               end if;
+               
+               alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);
+               
+               alu_result <= alu_result_v;
+               
+end process;
+
+end architecture shift_op;