Added missing signals to sensitivity and extended writeback

[calu.git] / cpu / src / exec_op / add_op_b.vhd

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index 331bb2968edf4bf5f52f20832d3d80a2c9de619a..44c1b928d01f411375fb2d6667ec6f7d87e77e31 100644 (file)
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -24,7 +24,7 @@ calc: process(left_operand, right_operand, alu_state, sub, addc)
 begin
                alu_result_v := alu_state;
                addcarry := (others => '0');
-               addcarry(0):= (alu_state.status.carry and addc) or sub;
+               addcarry(0):= (alu_state.status.carry and addc) or (sub and not(addc));
                if sub = '1' then
                        carry_res := unsigned('0' & left_operand)+unsigned('0' & not(right_operand))+addcarry;
                else