added pipe 2 reg, testbench, top_level_entity, ...

[calu.git] / cpu / src / decode_stage_b.vhd

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 54cf7284440f736dfcac200da4bf006ddb3944cd..fbaf0101d7804730f7ff60632e9fdae7f44dc765 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -13,7 +13,9 @@ architecture behav of decode_stage is
 signal instr_spl : instruction_rec;
 
 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
-signal reg1_mem_data, reg2_mem_data : gp_register_t;
+signal reg1_mem_data, reg2_mem_data, reg1_rd_data, reg2_rd_data : gp_register_t;
+signal dec_op_inst, dec_op_inst_nxt : dec_op;
+
 
 begin
 
@@ -52,13 +54,26 @@ begin
                rtw_rec.rtw_reg <= (others => '0');
                rtw_rec.rtw_reg1 <= '0';
                rtw_rec.rtw_reg2 <= '0';
+               rtw_rec.immediate <= (others => '0');
+               rtw_rec.imm_set <= '0';
+
+               dec_op_inst.condition <= (others => '0');
+               dec_op_inst.op_detail <= (others => '0');
+               dec_op_inst.brpr <= '0'; --branch_prediction_bit;
+               dec_op_inst.src1 <= (others => '0');
+               dec_op_inst.src2 <= (others => '0');
+               dec_op_inst.saddr1 <= (others => '0');
+               dec_op_inst.saddr2 <= (others => '0');
+               dec_op_inst.daddr <= (others => '0');
+
+
        elsif rising_edge(clk) then
                rtw_rec <= rtw_rec_nxt;
+               dec_op_inst <= dec_op_inst_nxt;
        end if;
        
 end process; 
 
-
 --     type dec_op is record
 --             condition : condition_t;
 --             op_group : op_info_t;
@@ -75,10 +90,30 @@ end process;
 --             
 --     end record;
 
-to_alu: process(instr_spl)
+-- output logic incl. bypassing reg-file
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
 
 begin
 
+       to_next_stage <= dec_op_inst;
+       to_next_stage.src1 <= reg1_rd_data;
+       to_next_stage.src2 <= reg2_rd_data;
+
+end process;
+
+
+-- fills output register
+to_next: process(instr_spl)
+
+begin
+       dec_op_inst_nxt.condition <= instr_spl.predicates;
+       dec_op_inst_nxt.op_detail <= instr_spl.op_detail;
+       dec_op_inst_nxt.brpr <= instr_spl.bp; --branch_prediction_bit;
+       dec_op_inst_nxt.src1 <= (others => '0');
+       dec_op_inst_nxt.src2 <= (others => '0');
+       dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
+       dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
+       dec_op_inst_nxt.daddr <= (others => '0');
 
 end process;
 
@@ -97,26 +132,35 @@ begin
        else
                reg2_rd_data <= reg2_mem_data;
        end if;
+
+       if (rtw_rec.imm_set = '1') then
+               reg2_rd_data <= rtw_rec.immediate;
+       end if;
 end process;
 
 
 -- async process: checks forward condition
-forward: process(instr_spl, reg_w_addr, reg_wr_data)
+forward: process(instr_spl, reg_w_addr, reg_wr_data, reg_we)
 
 begin
 
        rtw_rec_nxt.rtw_reg <= reg_wr_data;
        rtw_rec_nxt.rtw_reg1 <= '0';
        rtw_rec_nxt.rtw_reg2 <= '0';
+       rtw_rec_nxt.immediate <= (others => '0');
+       rtw_rec_nxt.imm_set <= '0';
 
-       rtw_rec_nxt.immediate <= instr_spl.immediate;
+       if (instr_spl.op_detail(IMM_OPT) = '1') then
+               rtw_rec_nxt.immediate <= instr_spl.immediate;
+               rtw_rec_nxt.imm_set <= '1';
+       end if;
 
        if (reg_w_addr = instr_spl.reg_src1_addr) then
-               rtw_rec_nxt.rtw_reg1 <= '1';
+               rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
        end if;
 
        if (reg_w_addr = instr_spl.reg_src2_addr) then
-               rtw_rec_nxt.rtw_reg2 <= '1';
+               rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
        end if;
 
 end process;