pipe2

[calu.git] / cpu / src / decode_stage_b.vhd

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 28c04c35aaf5aa0353af073505d90f28ffba4476..54cf7284440f736dfcac200da4bf006ddb3944cd 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -8,7 +8,6 @@ use work.core_pkg.all;
 use work.common_pkg.all;
 
 
-
 architecture behav of decode_stage is
 
 signal instr_spl : instruction_rec;
@@ -60,6 +59,29 @@ begin
 end process; 
 
 
+--     type dec_op is record
+--             condition : condition_t;
+--             op_group : op_info_t;
+--             op_detail : op_opt_t;
+--             brpr : std_logic;
+--             
+--             src1 : gp_register_t;
+--             src2 : gp_register_t;
+--             
+--             saddr1 : gp_addr_t;
+--             saddr2 : gp_addr_t;
+--             
+--             daddr   : gp_addr_t;
+--             
+--     end record;
+
+to_alu: process(instr_spl)
+
+begin
+
+
+end process;
+
 -- async process: decides between memory and read-through-write buffer on output
 output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
 
@@ -87,6 +109,8 @@ begin
        rtw_rec_nxt.rtw_reg1 <= '0';
        rtw_rec_nxt.rtw_reg2 <= '0';
 
+       rtw_rec_nxt.immediate <= instr_spl.immediate;
+
        if (reg_w_addr = instr_spl.reg_src1_addr) then
                rtw_rec_nxt.rtw_reg1 <= '1';
        end if;