added pipe 2 reg, testbench, top_level_entity, ...

[calu.git] / cpu / src / decode_stage.vhd

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 2b0cf49a62513e8c4060c39d4afca6ba2011977f..103822cb0463fef2d39433f637a01e5db047bede 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -27,10 +27,12 @@ entity decode_stage is
                        reg_we : in std_logic;
 
                --Data outputs
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t;
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
                        branch_prediction_res : out instruction_word_t;
-                       branch_prediction_bit : out std_logic
+                       branch_prediction_bit : out std_logic;
+
+                       to_next_stage : out dec_op
                        
                );