dt: some dependencies fixes, so it compiles with quartus

[calu.git] / cpu / src / core_top_s3e.vhd

diff --git a/cpu/src/core_top_s3e.vhd b/cpu/src/core_top_s3e.vhd
index 51465e5155b34f10259ccde7725fd7a6ffa84395..e047c62f8dbb665f1e20b4099475780850e768e2 100644 (file)
--- a/cpu/src/core_top_s3e.vhd
+++ b/cpu/src/core_top_s3e.vhd
@@ -67,7 +67,10 @@ architecture behav of core_top is
                 signal sys_res_n : std_logic;
 
                 signal int_req : interrupt_t;
-                
+
+                signal new_im_data : std_logic;
+                signal im_addr, im_data : gp_register_t;
+
                 signal vers, vers_nxt : exec2wb_rec;
 begin
 
@@ -89,7 +92,10 @@ begin
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
                        int_req => int_req,
-
+               -- instruction memory program port :D
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
                        prog_cnt => prog_cnt_pin                
@@ -151,8 +157,10 @@ begin
                 generic map('0', '1', "s3e")
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin,
-                               alu_jump_bit_pin,bus_tx, bus_rx, open, open, open, sseg0, sseg1, sseg2, sseg3, int_req);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+                               -- instruction memory program port :D
+                               new_im_data, im_addr, im_data,
+                               sseg0, sseg1, sseg2, sseg3, int_req);
 
 
 syn: process(sys_clk, sys_res)