default baudrate setting now in top level entity

[calu.git] / cpu / src / core_top_c2de1.vhd

diff --git a/cpu/src/core_top_c2de1.vhd b/cpu/src/core_top_c2de1.vhd
index adecfeea85896300d6ace14f9f8fde867ca6ce60..0d149c1a1a97c67c2c913554fec9ec356cc3231b 100644 (file)
--- a/cpu/src/core_top_c2de1.vhd
+++ b/cpu/src/core_top_c2de1.vhd
@@ -138,7 +138,7 @@ begin
 
                                                                         
           writeback_st : writeback_stage
-                generic map(RESET_VALUE, '1', "altera")
+                generic map(RESET_VALUE, '1', "altera", 434)
                 port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,