port(
--System input pins
+ sys_res : in std_logic;
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
architecture behav of core_top is
signal jump_result : instruction_addr_t;
- signal sys_res : std_logic;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
- sys_res <= '1';
+-- sys_res <= '1';
-- reg_wr_data <= reg_wr_data_pin;
end behav;