added soft reset

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index eafb605135bf9a5dcee5c06f88cfc2bb21e6b563..f3e132328db24cfdc16516be3954a6a24673f47a 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,12 +11,14 @@ entity core_top is
        port(
                --System input pins
                   sys_res : in std_logic;
+                       soft_res : in std_logic;
                        sys_clk : in std_logic;
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
                  -- uart
                        bus_tx : out std_logic;
                        bus_rx : in std_logic;
+                       led2 : out std_logic;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
@@ -63,8 +65,13 @@ architecture behav of core_top is
                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
                 
-                signal sync : std_logic_vector(1 to SYNC_STAGES);
-                signal sys_res_n : std_logic;
+                signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
+                signal sys_res_n, soft_res_n : std_logic;
+
+                signal int_req : interrupt_t;
+
+                signal new_im_data : std_logic;
+                signal im_addr, im_data : gp_register_t;
                 
                 signal vers, vers_nxt : exec2wb_rec;
 begin
@@ -80,16 +87,21 @@ begin
                --System inputs
                        clk => sys_clk, --: in std_logic;
                        reset => sys_res_n, --: in std_logic;
-               
+                       s_reset => soft_res_n,
                --Data inputs
                        jump_result => jump_result_pin, --: in instruction_addr_t;
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
-
+                       int_req => int_req,
+               -- instruction memory program port :D
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
-                       prog_cnt => prog_cnt_pin                
+                       prog_cnt => prog_cnt_pin,
+                       led2 => led2
                );
 
        decode_st : decode_stage
@@ -103,7 +115,7 @@ begin
                port map (
                --System inputs
                        clk => sys_clk, --: in std_logic;
-                       reset => sys_res_n, -- : in std_logic;
+                       reset => sys_res_n and soft_res_n, -- : in std_logic;
 
                --Data inputs
                        instruction => instruction_pin, --: in instruction_word_t;
@@ -121,7 +133,7 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
 
@@ -145,17 +157,20 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1')
-                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                generic map('0', '1', "altera", 2083)
+                port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+                               -- instruction memory program port :D
+                               new_im_data, im_addr, im_data,
+                               sseg0, sseg1, sseg2, sseg3, int_req);
 
 
-syn: process(sys_clk, sys_res)
+syn: process(sys_clk, sys_res, soft_res)
 
 begin
 
-       if sys_res = '0' then
+       if sys_res = '1' then
 --                     vers.result <= (others => '0');
 --                     vers.result_addr <= (others => '0');
 --                     vers.address <= (others => '0');
@@ -169,19 +184,25 @@ begin
 --                     vers.byte_s <= '0';
        
                sync <= (others => '0');
+               sync2 <= (others => '0');
        
        elsif rising_edge(sys_clk) then
 --             vers <= vers_nxt;
-                       sync(1) <= sys_res;
+                       sync(1) <= not sys_res;
                        for i in 2 to SYNC_STAGES loop
                                sync(i) <= sync(i - 1);
                        end loop;
-                               
+                       sync2(1) <= not soft_res;
+                       for i in 2 to SYNC_STAGES loop
+                               sync2(i) <= sync2(i - 1);
+                       end loop;
        end if;
+
        
 end process;
 
 sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
        
 --init : process(all)