modified: interfaces according to SP operation

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index bb9578936f77f1307fb83f91b983ddbaf144c095..d67243c4f9e2ae16d4302c47cbe5a7892af6d3ef 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -47,10 +47,12 @@ architecture behav of core_top is
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
+                                
+                                signal gpm_in_pin : ext_mod_rec;
+                                signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
 
-
 begin
 
        fetch_st : fetch_stage
@@ -105,8 +107,8 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
-                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+                port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
                 generic map('0', '1')