Added missing signals to sensitivity and extended writeback

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 5352332ddcc9744162ed4eaefa41bf07ea3bdc04..7ece8f1decf6b0e8768b396012ee180e33c613db 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -140,8 +140,8 @@ begin
 
                        writeback_st : writeback_stage
                 generic map('0', '1')
-                port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred, 
-                vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s,
+                port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);