added pipe 2 reg, testbench, top_level_entity, ...

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index a63616049cfa6dec151ab3649c00edda0cc505e9..7ec0743961062e2158db09df3d6cbbe669e657e8 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,9 +11,8 @@ entity core_top is
                --System input pins
                        sys_clk : in std_logic;
                        sys_res : in std_logic;
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t
 
+                       to_next_stage : out dec_op
                        
                );
 
@@ -30,6 +29,7 @@ architecture behav of core_top is
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
+
 --             signal reg1_rd_data_pin : gp_register_t;
 --             signal reg2_rd_data_pin : gp_register_t;
 
@@ -78,11 +78,9 @@ begin
                        reg_we => reg_we_pin, --: in std_logic;
 
                --Data outputs
-                       reg1_rd_data => reg1_rd_data, --: gp_register_t;
-                       reg2_rd_data => reg2_rd_data, --: gp_register_t;
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
-                       branch_prediction_bit => branch_prediction_bit_pin --: std_logic
-                       
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage
                );