-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
+ led2 : out std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
signal sys_res_n : std_logic;
signal int_req : interrupt_t;
+
+ signal new_im_data : std_logic;
+ signal im_addr, im_data : gp_register_t;
signal vers, vers_nxt : exec2wb_rec;
begin
--System inputs
clk => sys_clk, --: in std_logic;
reset => sys_res_n, --: in std_logic;
-
+ s_reset => '1',
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
prediction_result => prediction_result_pin, --: in instruction_addr_t;
branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
int_req => int_req,
-
+ -- instruction memory program port :D
+ new_im_data_in => new_im_data,
+ im_addr => im_addr,
+ im_data => im_data,
--Data outputs
instruction => instruction_pin, --: out instruction_word_t
- prog_cnt => prog_cnt_pin
+ prog_cnt => prog_cnt_pin,
+ led2 => led2
);
decode_st : decode_stage
--
writeback_st : writeback_stage
- generic map('0', '1')
+ generic map('0', '1', "altera")
port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3, int_req);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+ -- instruction memory program port :D
+ new_im_data, im_addr, im_data,
+ sseg0, sseg1, sseg2, sseg3, int_req);
syn: process(sys_clk, sys_res)
begin
- if sys_res = '0' then
+ if sys_res = '1' then
-- vers.result <= (others => '0');
-- vers.result_addr <= (others => '0');
-- vers.address <= (others => '0');
elsif rising_edge(sys_clk) then
-- vers <= vers_nxt;
- sync(1) <= sys_res;
+ sync(1) <= not sys_res;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;