--System inputs
clk : in std_logic;
reset : in std_logic;
+ s_reset : in std_logic;
--Data inputs
jump_result : in instruction_addr_t;
--Data outputs
instruction : out instruction_word_t;
- prog_cnt : out instruction_addr_t
+ prog_cnt : out instruction_addr_t;
+ -- debug
+ led2 : out std_logic
);
end component fetch_stage;
RESET_VALUE : std_logic;
-- active logic value
LOGIC_ACT : std_logic;
- FPGATYPE : string
+ FPGATYPE : string;
+ CLK_BAUD : integer
);
port(
--System inputs