subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
- subtype gp_addr_t is unsigned(REG_ADDR_WIDTH-1 downto 0);
+ subtype gp_addr_t is std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
+ op_detail : op_pot_t;
+
end record;
rtw_reg : gp_register_t;
rtw_reg1 : std_logic;
rtw_reg2 : std_logic;
+ immediate : gp_register_t;
end record;