bugfix: sp operation first approach.

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index c46f9e5a926a1bc1ca9dd2bf4d96caf19f5e08e4..b0bf5a4419d68a60f2014a75e741bfc55ce399d4 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -41,7 +41,7 @@ begin
        shift_inst : entity work.exec_op(shift_op)\r
        port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
 \r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
@@ -63,6 +63,10 @@ begin
         addr <= add_result.result;\r
         data <= right_operand;\r
        \r
+       pinc <= '0';\r
+       pwr_en <= '0';\r
+       paddr <= (others =>'0');\r
+       \r
        result_v.result := add_result.result;\r
 \r
        case cond is\r