Seperation to differen execute operations.

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 533ed7f8742b08082ed3b477bce0d90295371dfe..511b15426f36e640b167936aea137bc07290dd9c 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -2,37 +2,139 @@ library IEEE;
 use IEEE.std_logic_1164.all;\r
 use IEEE.numeric_std.all;\r
 \r
-use work.core_pkg.all;\r
 use work.alu_pkg.all;\r
 \r
-architecture behaviour of alu is\r
 \r
+architecture behaviour of alu is\r
+       component exec_op is\r
+       port(\r
+               --System inputs\r
+               \r
+               clk : in std_logic;\r
+               reset : in std_logic;\r
+               --operation inputs\r
+               left_operand : in gp_register_t;\r
+               right_operand : in gp_register_t;\r
+               op_detail  : in op_opt_t;\r
+               alu_state  : in alu_result_rec;\r
+               alu_result : out alu_result_rec\r
+       );                      \r
+       end component exec_op;\r
+       \r
+       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+       \r
 begin\r
 \r
-syn: process(sys_clk, reset)\r
+       add_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+       \r
+       and_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
+       or_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
+       xor_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+       \r
+       shift_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
 \r
+calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+       variable result_v : alu_result_rec;\r
+       variable res_prod : std_logic;\r
+       variable cond_met : std_logic;\r
+       variable mem_en : std_logic;\r
 begin\r
-\r
-       if (reset = RESET_VALUE) then\r
-                               \r
-       elsif rising_edge(sys_clk) then\r
-               \r
+       result_v := alu_state;\r
+       \r
+       result_v.result := add_result.result;\r
+       res_prod := '1';\r
+       mem_en := '0';\r
+       \r
+       case condition is\r
+       when COND_NZERO =>\r
+               cond_met := not(alu_state.status.zero);\r
+       when COND_ZERO =>\r
+               cond_met := alu_state.status.zero;\r
+       when COND_NOFLO =>\r
+               cond_met := not(alu_state.status.oflo);\r
+       when COND_OFLO =>\r
+               cond_met := alu_state.status.oflo;\r
+       when COND_NCARRY =>\r
+               cond_met := not(alu_state.status.carry);\r
+       when COND_CARRY =>\r
+               cond_met := alu_state.status.carry;\r
+       when COND_NSIGN =>\r
+               cond_met := not(alu_state.status.sign);\r
+       when COND_SIGN =>\r
+               cond_met := alu_state.status.sign;\r
+       when COND_ABOVE =>\r
+               cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);\r
+       when COND_BEQ =>\r
+               cond_met := alu_state.status.carry or alu_state.status.zero;\r
+       when COND_GEQ =>\r
+               cond_met := not(alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_LT =>\r
+               cond_met := alu_state.status.sign xor alu_state.status.oflo;\r
+       when COND_GT =>\r
+               cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_LEQ =>\r
+               cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_ALWAYS =>\r
+               cond_met := '1';\r
+       when COND_NEVER =>\r
+               cond_met := '0';\r
+       end case;\r
+       \r
+       case op_group is\r
+       when ADDSUB_OP =>\r
+               result_v := add_result;\r
+       when AND_OP =>\r
+               result_v := and_result;\r
+       when OR_OP =>\r
+               result_v := or_result;\r
+       when XOR_OP =>\r
+               result_v := xor_result;\r
+       when SHIFT_OP =>\r
+               result_v := shift_result;\r
+       end case;\r
+       \r
+       if result_v.result = REG_ZERO then\r
+               result_v.status.zero := '1';\r
        end if;\r
        \r
-end process syn; \r
-\r
-\r
-nxt_calc: process(sys_clk, reset)\r
-\r
-begin\r
+       result_v.status.sign := result_v.result(gp_register_t'high);\r
 \r
+       if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then\r
+               result_v.status := alu_state.status;\r
+       end if;\r
        \r
-       case new_op is\r
-       when ADD_SUB =>\r
-               \r
-       when others => null;\r
-       end case;\r
+       result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
+       result_v.mem_en := mem_en and cond_met;\r
+       \r
+       alu_result <= result_v;\r
        \r
-end process nxt_calc; \r
+end process calc; \r
 \r
 end architecture behaviour;\r
+\r
+configuration alu_cfg of alu is\r
+\r
+       for behaviour\r
+               for add_inst : exec_op \r
+                       use entity work.exec_op(add_op);\r
+               end for;\r
+               for and_inst : exec_op \r
+                       use entity work.exec_op(and_op);\r
+               end for;\r
+               for or_inst : exec_op\r
+                       use entity work.exec_op(or_op);\r
+               end for;\r
+               for xor_inst : exec_op\r
+                       use entity work.exec_op(xor_op);\r
+               end for;\r
+               for shift_inst : exec_op\r
+                       use entity work.exec_op(shift_op);\r
+               end for;\r
+       end for;\r
+               \r
+end configuration alu_cfg;\r