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cpu: ext_reg switch bug FIX by markus
[calu.git]
/
cpu
/
src
/
alu_b.vhd
diff --git
a/cpu/src/alu_b.vhd
b/cpu/src/alu_b.vhd
index 746fbc3489e85f38a74e287224d97e8e7f481b9d..60a14bf867acc3aae5c85484d14c8f3b79581a9e 100755
(executable)
--- a/
cpu/src/alu_b.vhd
+++ b/
cpu/src/alu_b.vhd
@@
-122,19
+122,14
@@
begin
case op_group is
when ADDSUB_OP =>
result_v := add_result;
case op_group is
when ADDSUB_OP =>
result_v := add_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when AND_OP =>
result_v := and_result;
when AND_OP =>
result_v := and_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when OR_OP =>
result_v := or_result;
when OR_OP =>
result_v := or_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when XOR_OP =>
result_v := xor_result;
when XOR_OP =>
result_v := xor_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when SHIFT_OP =>
result_v := shift_result;
when SHIFT_OP =>
result_v := shift_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when LDST_OP =>
res_prod := '0';
mem_op := '1';
when LDST_OP =>
res_prod := '0';
mem_op := '1';
@@
-155,7
+150,6
@@
begin
res_prod := '1';
mem_op := '0';
res_prod := '1';
mem_op := '0';
- addr(DATA_ADDR_WIDTH + 3) <= '0';
end if;
if op_detail(ST_OPT) = '1' then
mem_en := '1';
end if;
if op_detail(ST_OPT) = '1' then
mem_en := '1';