cpu: ext_reg switch bug FIX by markus

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 746fbc3489e85f38a74e287224d97e8e7f481b9d..60a14bf867acc3aae5c85484d14c8f3b79581a9e 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -122,19 +122,14 @@ begin
        case op_group is
        when ADDSUB_OP =>
                result_v := add_result;
-               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when AND_OP =>
                result_v := and_result;
-               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when OR_OP =>
                result_v := or_result;
-               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when XOR_OP =>
                result_v := xor_result;
-               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when SHIFT_OP =>
                result_v := shift_result;
-               addr(DATA_ADDR_WIDTH + 3) <= '0';
    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';
@@ -155,7 +150,6 @@ begin
 
                         res_prod := '1';
                         mem_op := '0';
-                                                               addr(DATA_ADDR_WIDTH + 3) <= '0';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 569f2c68ed2e280c0367745ce07ab06ee2aa8d38..6d03873d9dff12c22bf05af03b823dedc84409da 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -276,7 +276,7 @@ begin
        if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_out := data_ram_read;
        else
-               reg_we_v := reg_we_v and ext_anysel;
+               reg_we_v := reg_we_v and (ext_anysel or not(wb_reg.dmem_en));
                data_out := data_ram_read_ext;
        end if;