uart: bugfix fuer busy reset

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index 885a80f38a8ab1f38299e29f8cf5fc92824427fa..fc2ff124c6ced39c40f543283521e879384df1ed 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -131,13 +131,15 @@ add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_rx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_tx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
 
 
 run 5000 ns