lustiger modelsim fix...

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index c781ad4b771bb90ef5d63dee70216a80a337845b..f2e2b79dabcb364f87f1a505f8b6ab04c00e8467 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -5,6 +5,8 @@ vcom -work work ../src/mem_pkg.vhd
 vcom -work work ../src/rom.vhd
 vcom -work work ../src/rom_b.vhd
 vcom -work work ../src/r_w_ram.vhd
+vcom -work work ../src/r_w_ram_be.vhd
+vcom -work work ../src/r_w_ram_be_b.vhd
 vcom -work work ../src/r_w_ram_b.vhd
 vcom -work work ../src/r2_w_ram.vhd
 vcom -work work ../src/r2_w_ram_b.vhd
@@ -74,6 +76,7 @@ add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_add
 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
 add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
+add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/rom_ram
 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
 
 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
@@ -130,12 +133,25 @@ add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/im_addr
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/im_data
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/new_im_data_out
-add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/im_addr
-add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/im_data
-add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/new_im_data_in
-
-
-run 5000 ns
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_rx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_tx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt
+
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
+add wave  -group test -radix hexadecimal /pipeline_tb/exec_st/dmem_write_en
+
+run 100000 ns