writeback_stage: differenzieren zwischen memory und extension geht ( btw wer sich...

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index a4baa8d9ea33637cf5f6aac8453e7a9927f322cb..5ef159affd500cb6c1360081cabdf4915eb7ea49 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -120,8 +120,10 @@ add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 
-
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ram_data
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config