timer: added as extension modul

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index f2e2b79dabcb364f87f1a505f8b6ab04c00e8467..07def81a9009c77c72bd2fa99fb4f176eba568bb 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -49,6 +49,10 @@ vcom -work work ../src/extension_7seg_pkg.vhd
 vcom -work work ../src/extension_7seg.vhd
 vcom -work work ../src/extension_7seg_b.vhd
 
+vcom -work work ../src/extension_timer_pkg.vhd
+vcom -work work ../src/extension_timer.vhd
+vcom -work work ../src/extension_timer_b.vhd
+
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/rs232_tx.vhd
 vcom -work work ../src/rs232_tx_arc.vhd
@@ -144,6 +148,11 @@ add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_dat
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt
 
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val_nxt
+
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en