added pipe 2 reg, testbench, top_level_entity, ...

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 8682728cf91a83582a34e48a36992704d6c761cf..da92a48b390eaa2b7cc894f55eb8d925ef31251c 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -27,6 +27,7 @@ add wave  -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
 
 add wave  -radix hexadecimal /pipeline_tb/decode_st/instruction
 add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
+add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec