fibonacci tested rc1, 107 cycles, 1k2le, 57MHz

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 321364ee213fdf6f071ff19530c573929369edc0..cf8d69c0f8ce7b5389d37f2c6a422eb47935274a 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -72,5 +72,6 @@ add wave  -radix hexadecimal /pipeline_tb/addr_pin
 add wave  -radix hexadecimal /pipeline_tb/data_pin
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave  -radix decimal     /pipeline_tb/cycle_cnt
 
-run 5000 ns
+run 10000 ns