uart und extension anbindung

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index a6f71435596cb6d2abee2a02dbd87993f36ae04b..a52d799045dbf306a9cffae9a84da3ee2ae141e6 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -87,6 +87,10 @@ add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_addr
+
+add wave  -radix hexadecimal /pipeline_tb/tx_pin
+add wave  -radix hexadecimal /pipeline_tb/rx_pin
+
 add wave  -radix decimal     /pipeline_tb/cycle_cnt
 
 run 10000 ns