writeback_stage: differenzieren zwischen memory und extension geht ( btw wer sich...

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index aeb749146372f341823df2d433fab36b37c2455e..9a4c3fe0a01afc76ddc63d3c50b059284f037fd0 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -9,6 +9,13 @@ vcom -work work ../src/r2_w_ram_b.vhd
 vcom -work work ../src/common_pkg.vhd
 vcom -work work ../src/extension_pkg.vhd
 vcom -work work ../src/extension_uart_pkg.vhd
+vcom -work work ../src/extension_uart.vhd
+vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/rs232_tx.vhd
+vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/rs232_rx.vhd
+vcom -work work ../src/rs232_rx_arc.vhd
+
 vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/decoder.vhd
 vcom -work work ../src/decoder_b.vhd
@@ -73,6 +80,8 @@ add wave  -radix hexadecimal /pipeline_tb/addr_pin
 add wave  -radix hexadecimal /pipeline_tb/data_pin
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_addr
 add wave  -radix decimal     /pipeline_tb/cycle_cnt
 
 run 10000 ns