spartan3e/Makefile

   1 SHELL := bash
   2
   3 VHDL_DIR := ../cpu/src
   4 PROJ_VHDL = \
   5         core_top_s3e.vhd \
   6         alu_b.vhd \
   7         alu_pkg.vhd \
   8         alu.vhd \
   9         common_pkg.vhd \
  10         core_pkg.vhd \
  11         decoder_b.vhd \
  12         decoder.vhd \
  13         decode_stage_b.vhd \
  14         decode_stage.vhd \
  15         exec_op/add_op_b.vhd \
  16         exec_op/and_op_b.vhd \
  17         exec_op/or_op_b.vhd \
  18         exec_op/shift_op_b.vhd \
  19         exec_op/xor_op_b.vhd \
  20         exec_op.vhd \
  21         execute_stage_b.vhd \
  22         execute_stage.vhd \
  23         extension_b.vhd \
  24         extension_interrupt_b.vhd \
  25         extension_interrupt.vhd \
  26         extension_pkg.vhd \
  27         extension_uart_b.vhd \
  28         extension_uart_pkg.vhd \
  29         extension_uart.vhd \
  30         extension_7seg_b.vhd \
  31         extension_7seg_pkg.vhd \
  32         extension_7seg.vhd \
  33         extension_imp_b.vhd \
  34         extension_imp_pkg.vhd \
  35         extension_imp.vhd \
  36         extension.vhd \
  37         fetch_stage_b.vhd \
  38         fetch_stage.vhd \
  39         mem_pkg.vhd \
  40         r2_w_ram_b.vhd \
  41         r2_w_ram.vhd \
  42         rom_b.vhd \
  43         rom.vhd \
  44         rs232_rx_arc.vhd \
  45         rs232_rx.vhd \
  46         rs232_tx_arc.vhd \
  47         rs232_tx.vhd \
  48         ram_xilinx.vhd \
  49         ram_xilinx_b.vhd \
  50         r_w_ram_b.vhd \
  51         r_w_ram.vhd \
  52         rw_r_ram_b.vhd \
  53         rw_r_ram.vhd \
  54         writeback_stage_b.vhd \
  55         writeback_stage.vhd
  56
  57 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
  58
  59 NAME := core_top
  60
  61
  62 all: generated/$(NAME).mcs
  63
  64 generated:
  65         rm -rf generated
  66         mkdir generated
  67
  68 clean:
  69         rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
  70         rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
  71         rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
  72         rm -f *.bld *.ncd *.twr *.drc
  73         rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
  74         rm -rf xst $(NAME).prj
  75         rm -rf generated/
  76         rm -rf xlnx_auto_0_xdb _xmsgs
  77
  78 #Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
  79
  80 # create an ISE project file from the list of VHDL files
  81 $(NAME).prj: $(PROJ_VHDL)
  82         echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
  83
  84 bitfile: generated step0 step1 step2 step3 step4 step5
  85
  86 step0: $(NAME).prj
  87         xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
  88 step1:
  89         ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
  90 step2:
  91         map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
  92 step3:
  93         par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
  94 step4:
  95         trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
  96 step5:
  97         bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
  98
  99 generated/$(NAME).bit: bitfile
 100
 101 jtag: generated/$(NAME).bit
 102         impact -batch ISE_scripts/loadjtag.cmds
 103
 104 jtag_brv1: s3e_bootrom_v1.bit
 105         impact -batch ISE_scripts/loadjtag_brv1.cmds
 106
 107 mcs: generated/$(NAME).bit
 108         impact -batch ISE_scripts/makeprom.cmds
 109
 110 generated/$(NAME).mcs: mcs
 111
 112 load: generated/$(NAME).mcs
 113         impact -batch ISE_scripts/loadprom.cmds
 114
 115 impact:
 116         impact
 117
 118 ise: $(NAME).prj
 119         ise