15 exec_op/add_op_b.vhd \
16 exec_op/and_op_b.vhd \
18 exec_op/shift_op_b.vhd \
19 exec_op/xor_op_b.vhd \
24 extension_interrupt_b.vhd \
25 extension_interrupt.vhd \
26 extension_timer_b.vhd \
27 extension_timer_pkg.vhd \
30 extension_uart_b.vhd \
31 extension_uart_pkg.vhd \
33 extension_7seg_b.vhd \
34 extension_7seg_pkg.vhd \
37 extension_imp_pkg.vhd \
57 writeback_stage_b.vhd \
60 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
65 all: generated/$(NAME).mcs
72 rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
73 rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
74 rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
75 rm -f *.bld *.ncd *.twr *.drc
76 rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
77 rm -rf xst $(NAME).prj
79 rm -rf xlnx_auto_0_xdb _xmsgs
81 #Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
83 # create an ISE project file from the list of VHDL files
84 $(NAME).prj: $(PROJ_VHDL)
85 echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
87 bitfile: generated step0 step1 step2 step3 step4 step5
90 xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
92 ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
94 map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
96 par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
98 trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
100 bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
102 generated/$(NAME).bit: bitfile
104 jtag: generated/$(NAME).bit
105 impact -batch ISE_scripts/loadjtag.cmds
107 jtag_brv1: s3e_bootrom_v1.bit
108 impact -batch ISE_scripts/loadjtag_brv1.cmds
110 mcs: generated/$(NAME).bit
111 impact -batch ISE_scripts/makeprom.cmds
113 generated/$(NAME).mcs: mcs
115 load: generated/$(NAME).mcs
116 impact -batch ISE_scripts/loadprom.cmds