dt/dt.drc.rpt

   1 Design Assistant report for dt
   2 Mon Dec 20 17:39:01 2010
   3 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
   4
   5
   6 ---------------------
   7 ; Table of Contents ;
   8 ---------------------
   9   1. Legal Notice
  10   2. Design Assistant Summary
  11   3. Design Assistant Settings
  12   4. High Violations
  13   5. Medium Violations
  14   6. Information only Violations
  15   7. Design Assistant Messages
  16
  17
  18
  19 ----------------
  20 ; Legal Notice ;
  21 ----------------
  22 Copyright (C) 1991-2010 Altera Corporation
  23 Your use of Altera Corporation's design tools, logic functions
  24 and other software and tools, and its AMPP partner logic
  25 functions, and any output files from any of the foregoing
  26 (including device programming or simulation files), and any
  27 associated documentation or information are expressly subject
  28 to the terms and conditions of the Altera Program License
  29 Subscription Agreement, Altera MegaCore Function License
  30 Agreement, or other applicable license agreement, including,
  31 without limitation, that your use is for the sole purpose of
  32 programming logic devices manufactured by Altera and sold by
  33 Altera or its authorized distributors.  Please refer to the
  34 applicable agreement for further details.
  35
  36
  37
  38 +-------------------------------------------------------------------------+
  39 ; Design Assistant Summary                                                ;
  40 +-----------------------------------+-------------------------------------+
  41 ; Design Assistant Status           ; Analyzed - Mon Dec 20 17:39:01 2010 ;
  42 ; Revision Name                     ; dt                                  ;
  43 ; Top-level Entity Name             ; core_top                            ;
  44 ; Family                            ; Cyclone                             ;
  45 ; Total Critical Violations         ; 0                                   ;
  46 ; Total High Violations             ; 12                                  ;
  47 ; - Rule S102                       ; 12                                  ;
  48 ; Total Medium Violations           ; 1                                   ;
  49 ; - Rule R102                       ; 1                                   ;
  50 ; Total Information only Violations ; 99                                  ;
  51 ; - Rule T101                       ; 49                                  ;
  52 ; - Rule T102                       ; 50                                  ;
  53 +-----------------------------------+-------------------------------------+
  54
  55
  56 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
  57 ; Design Assistant Settings                                                                                                                                                                                                                                                                                ;
  58 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
  59 ; Option                                                                                                                                                                                                                                                                               ; Setting      ; To ;
  60 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
  61 ; Design Assistant mode                                                                                                                                                                                                                                                                ; Post-Fitting ;    ;
  62 ; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                        ; 25           ;    ;
  63 ; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                    ; 30           ;    ;
  64 ; Minimum number of node fan-out                                                                                                                                                                                                                                                       ; 30           ;    ;
  65 ; Maximum number of nodes to report                                                                                                                                                                                                                                                    ; 50           ;    ;
  66 ; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                 ; On           ;    ;
  67 ; Rule C102: Logic cell should not be used to generate an inverted clock signal                                                                                                                                                                                                        ; On           ;    ;
  68 ; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power                                                                                                                                                                          ; On           ;    ;
  69 ; Rule C104: Clock signal source should drive only clock input ports                                                                                                                                                                                                                   ; On           ;    ;
  70 ; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;    ;
  71 ; Rule C106: Clock signal source should not drive registers triggered by different clock edges                                                                                                                                                                                         ; On           ;    ;
  72 ; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                         ; On           ;    ;
  73 ; Rule R102: External reset signals should be synchronized using two cascaded registers                                                                                                                                                                                                ; On           ;    ;
  74 ; Rule R103: External reset signal should be correctly synchronized                                                                                                                                                                                                                    ; On           ;    ;
  75 ; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized                                                                                                                                                  ; On           ;    ;
  76 ; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                            ; On           ;    ;
  77 ; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                     ; On           ;    ;
  78 ; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                             ; On           ;    ;
  79 ; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                             ; On           ;    ;
  80 ; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                           ; On           ;    ;
  81 ; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                    ; On           ;    ;
  82 ; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                         ; On           ;    ;
  83 ; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                           ; On           ;    ;
  84 ; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                         ; On           ;    ;
  85 ; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                      ; On           ;    ;
  86 ; Rule A108: Design should not contain latches                                                                                                                                                                                                                                         ; On           ;    ;
  87 ; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                             ; On           ;    ;
  88 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                ; On           ;    ;
  89 ; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source                                                                                                                                                                              ; On           ;    ;
  90 ; Rule S104: Clock port and any other port of a register should not be driven by the same signal source                                                                                                                                                                                ; On           ;    ;
  91 ; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                        ; On           ;    ;
  92 ; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                 ; On           ;    ;
  93 ; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                              ; On           ;    ;
  94 ; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                        ; Off          ;    ;
  95 ; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                   ; Off          ;    ;
  96 ; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                     ; Off          ;    ;
  97 ; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                         ; Off          ;    ;
  98 ; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                        ; Off          ;    ;
  99 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
 100
 101
 102 +---------------------------------------------------------------------------------------------------------------------------------------------------------------+
 103 ; High Violations                                                                                                                                               ;
 104 +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+
 105 ; Rule name                                                                                                             ; Name                                  ;
 106 +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+
 107 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; execute_stage:exec_st|reg.alu_jump    ;
 108 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 109 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0]  ;
 110 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 111 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[1]  ;
 112 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 113 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2]  ;
 114 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 115 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[3]  ;
 116 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 117 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4]  ;
 118 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 119 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[5]  ;
 120 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 121 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6]  ;
 122 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 123 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[7]  ;
 124 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 125 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[8]  ;
 126 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 127 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[9]  ;
 128 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 129 ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[10] ;
 130 ;  Synchronous and reset port source node(s) list                                                                       ; sys_res                               ;
 131 +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+
 132
 133
 134 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 135 ; Medium Violations                                                                                                                                                       ;
 136 +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
 137 ; Rule name                                                                             ; Name                                                                            ;
 138 +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
 139 ; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res                                                                         ;
 140 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1]  ;
 141 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2]  ;
 142 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3]  ;
 143 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4]  ;
 144 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5]  ;
 145 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6]  ;
 146 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7]  ;
 147 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8]  ;
 148 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9]  ;
 149 ;  Reset signal destination node(s) list                                                ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ;
 150 +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
 151
 152
 153 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 154 ; Information only Violations                                                                                                                                                                 ;
 155 +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
 156 ; Rule name                                                        ; Name                                                                                                           ; Fan-Out ;
 157 +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
 158 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19                                                                      ; 96      ;
 159 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en                                                                    ; 63      ;
 160 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3                                                                        ; 53      ;
 161 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[0]~25                                                                      ; 100     ;
 162 ; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk                                                                                                        ; 569     ;
 163 ; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res                                                                                                        ; 549     ;
 164 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set                                                                         ; 65      ;
 165 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~13                                                                      ; 42      ;
 166 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0                             ; 32      ;
 167 ; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND                                                                                                           ; 208     ;
 168 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16                                          ; 33      ;
 169 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0                                                                    ; 32      ;
 170 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1                                                                    ; 32      ;
 171 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2                                                                    ; 32      ;
 172 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3                                                                    ; 32      ;
 173 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5                                                                    ; 32      ;
 174 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6                                                                    ; 32      ;
 175 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7                                                                    ; 32      ;
 176 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8                                                                   ; 32      ;
 177 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9                                                                   ; 32      ;
 178 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10                                                                  ; 32      ;
 179 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP                                                            ; 60      ;
 180 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1]                                                                ; 109     ;
 181 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0                                                                   ; 42      ;
 182 ; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63      ;
 183 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP                                                           ; 56      ;
 184 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP                                                          ; 50      ;
 185 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13]                                                                ; 34      ;
 186 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[3]~22                                                                      ; 71      ;
 187 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]                                                                ; 78      ;
 188 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_out~2                                                                        ; 80      ;
 189 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072                                                         ; 71      ;
 190 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16                                                                      ; 75      ;
 191 ; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1  ; 33      ;
 192 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT                         ; 51      ;
 193 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0                                                ; 31      ;
 194 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2                                            ; 32      ;
 195 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3]                                                                 ; 39      ;
 196 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2]                                                                 ; 64      ;
 197 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0                                          ; 32      ;
 198 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP                                                           ; 40      ;
 199 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2                                                                        ; 32      ;
 200 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2                                                                      ; 31      ;
 201 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1                                                                        ; 32      ;
 202 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP                                                             ; 33      ;
 203 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP                                                              ; 64      ;
 204 ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP                                                             ; 33      ;
 205 ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0                                                                 ; 35      ;
 206 ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP                        ; 35      ;
 207 ; Rule T102: Top nodes with the highest number of fan-outs         ; sys_clk                                                                                                        ; 569     ;
 208 ; Rule T102: Top nodes with the highest number of fan-outs         ; sys_res                                                                                                        ; 549     ;
 209 ; Rule T102: Top nodes with the highest number of fan-outs         ; ~GND                                                                                                           ; 208     ;
 210 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_detail[1]                                                                ; 109     ;
 211 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|right_operand[0]~25                                                                      ; 100     ;
 212 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|right_operand[1]~19                                                                      ; 96      ;
 213 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_out~2                                                                        ; 80      ;
 214 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_detail[3]                                                                ; 78      ;
 215 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|right_operand[2]~16                                                                      ; 75      ;
 216 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|right_operand[3]~22                                                                      ; 71      ;
 217 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072                                                         ; 71      ;
 218 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|rtw_rec.imm_set                                                                         ; 65      ;
 219 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP                                                              ; 64      ;
 220 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|wb_reg.address[2]                                                                 ; 64      ;
 221 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|wb_reg.dmem_en                                                                    ; 63      ;
 222 ; Rule T102: Top nodes with the highest number of fan-outs         ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63      ;
 223 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP                                                            ; 60      ;
 224 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP                                                           ; 56      ;
 225 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|left_operand[5]~3                                                                        ; 53      ;
 226 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT                         ; 51      ;
 227 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP                                                          ; 50      ;
 228 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|right_operand[1]~13                                                                      ; 42      ;
 229 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|alu:alu_inst|WideOr2~0                                                                   ; 42      ;
 230 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP                                                           ; 40      ;
 231 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|wb_reg.address[3]                                                                 ; 39      ;
 232 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP                        ; 35      ;
 233 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|alu:alu_inst|Selector0~0                                                                 ; 35      ;
 234 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|wb_reg.address[13]                                                                ; 34      ;
 235 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16                                          ; 33      ;
 236 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP                                                             ; 33      ;
 237 ; Rule T102: Top nodes with the highest number of fan-outs         ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1  ; 33      ;
 238 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP                                                             ; 33      ;
 239 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2                                            ; 32      ;
 240 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[2]~0                                                                    ; 32      ;
 241 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[3]~1                                                                    ; 32      ;
 242 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|rtw_rec.rtw_reg2                                                                        ; 32      ;
 243 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[7]~5                                                                    ; 32      ;
 244 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[8]~6                                                                    ; 32      ;
 245 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[9]~7                                                                    ; 32      ;
 246 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[4]~2                                                                    ; 32      ;
 247 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|rtw_rec.rtw_reg1                                                                        ; 32      ;
 248 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[10]~8                                                                   ; 32      ;
 249 ; Rule T102: Top nodes with the highest number of fan-outs         ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0                             ; 32      ;
 250 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[11]~9                                                                   ; 32      ;
 251 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0                                          ; 32      ;
 252 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[5]~3                                                                    ; 32      ;
 253 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|data_addr[12]~10                                                                  ; 32      ;
 254 ; Rule T102: Top nodes with the highest number of fan-outs         ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0                                                ; 31      ;
 255 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|alu:alu_inst|calc~2                                                                      ; 31      ;
 256 ; Rule T102: Top nodes with the highest number of fan-outs         ; execute_stage:exec_st|alu:alu_inst|pwr_en~4                                                                    ; 30      ;
 257 +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
 258
 259
 260 +---------------------------+
 261 ; Design Assistant Messages ;
 262 +---------------------------+
 263 Info: *******************************************************************
 264 Info: Running Quartus II Design Assistant
 265     Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
 266     Info: Processing started: Mon Dec 20 17:38:59 2010
 267 Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off dt -c dt
 268 Critical Warning: Synopsys Design Constraints File file not found: 'dt.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 269 Info: No user constrained base clocks found in the design
 270 Critical Warning: (High) Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source. Found 12 node(s) related to this rule.
 271     Critical Warning: Node  "execute_stage:exec_st|reg.alu_jump"
 272     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[0]"
 273     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[1]"
 274     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[2]"
 275     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[3]"
 276     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[4]"
 277     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[5]"
 278     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[6]"
 279     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[7]"
 280     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[8]"
 281     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[9]"
 282     Critical Warning: Node  "fetch_stage:fetch_st|instr_r_addr[10]"
 283 Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.
 284     Warning: Node  "sys_res"
 285 Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 49 node(s) with highest fan-out.
 286     Info: Node  "execute_stage:exec_st|right_operand[1]~19"
 287     Info: Node  "writeback_stage:writeback_st|wb_reg.dmem_en"
 288     Info: Node  "execute_stage:exec_st|left_operand[5]~3"
 289     Info: Node  "execute_stage:exec_st|right_operand[0]~25"
 290     Info: Node  "sys_clk"
 291     Info: Node  "sys_res"
 292     Info: Node  "decode_stage:decode_st|rtw_rec.imm_set"
 293     Info: Node  "execute_stage:exec_st|right_operand[1]~13"
 294     Info: Node  "decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0"
 295     Info: Node  "~GND"
 296     Info: Node  "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16"
 297     Info: Node  "writeback_stage:writeback_st|data_addr[2]~0"
 298     Info: Node  "writeback_stage:writeback_st|data_addr[3]~1"
 299     Info: Node  "writeback_stage:writeback_st|data_addr[4]~2"
 300     Info: Node  "writeback_stage:writeback_st|data_addr[5]~3"
 301     Info: Node  "writeback_stage:writeback_st|data_addr[7]~5"
 302     Info: Node  "writeback_stage:writeback_st|data_addr[8]~6"
 303     Info: Node  "writeback_stage:writeback_st|data_addr[9]~7"
 304     Info: Node  "writeback_stage:writeback_st|data_addr[10]~8"
 305     Info: Node  "writeback_stage:writeback_st|data_addr[11]~9"
 306     Info: Node  "writeback_stage:writeback_st|data_addr[12]~10"
 307     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP"
 308     Info: Node  "decode_stage:decode_st|dec_op_inst.op_detail[1]"
 309     Info: Node  "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
 310     Info: Node  "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23"
 311     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP"
 312     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP"
 313     Info: Node  "writeback_stage:writeback_st|wb_reg.address[13]"
 314     Info: Node  "execute_stage:exec_st|right_operand[3]~22"
 315     Info: Node  "decode_stage:decode_st|dec_op_inst.op_detail[3]"
 316     Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
 317 Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
 318     Info: Node  "sys_clk"
 319     Info: Node  "sys_res"
 320     Info: Node  "~GND"
 321     Info: Node  "decode_stage:decode_st|dec_op_inst.op_detail[1]"
 322     Info: Node  "execute_stage:exec_st|right_operand[0]~25"
 323     Info: Node  "execute_stage:exec_st|right_operand[1]~19"
 324     Info: Node  "writeback_stage:writeback_st|data_out~2"
 325     Info: Node  "decode_stage:decode_st|dec_op_inst.op_detail[3]"
 326     Info: Node  "execute_stage:exec_st|right_operand[2]~16"
 327     Info: Node  "execute_stage:exec_st|right_operand[3]~22"
 328     Info: Node  "decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072"
 329     Info: Node  "decode_stage:decode_st|rtw_rec.imm_set"
 330     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.OR_OP"
 331     Info: Node  "writeback_stage:writeback_st|wb_reg.address[2]"
 332     Info: Node  "writeback_stage:writeback_st|wb_reg.dmem_en"
 333     Info: Node  "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23"
 334     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP"
 335     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP"
 336     Info: Node  "execute_stage:exec_st|left_operand[5]~3"
 337     Info: Node  "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT"
 338     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP"
 339     Info: Node  "execute_stage:exec_st|right_operand[1]~13"
 340     Info: Node  "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
 341     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP"
 342     Info: Node  "writeback_stage:writeback_st|wb_reg.address[3]"
 343     Info: Node  "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP"
 344     Info: Node  "execute_stage:exec_st|alu:alu_inst|Selector0~0"
 345     Info: Node  "writeback_stage:writeback_st|wb_reg.address[13]"
 346     Info: Node  "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16"
 347     Info: Node  "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP"
 348     Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
 349 Info: Design Assistant information: finished post-fitting analysis of current design -- generated 99 information messages and 13 warning messages
 350 Info: Quartus II Design Assistant was successful. 0 errors, 16 warnings
 351     Info: Peak virtual memory: 195 megabytes
 352     Info: Processing ended: Mon Dec 20 17:39:01 2010
 353     Info: Elapsed time: 00:00:02
 354     Info: Total CPU time (on all processors): 00:00:02
 355
 356