dt.tcl

   1 # Copyright (C) 1991-2010 Altera Corporation
   2 # Your use of Altera Corporation's design tools, logic functions
   3 # and other software and tools, and its AMPP partner logic
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   5 # (including device programming or simulation files), and any
   6 # associated documentation or information are expressly subject
   7 # to the terms and conditions of the Altera Program License
   8 # Subscription Agreement, Altera MegaCore Function License
   9 # Agreement, or other applicable license agreement, including,
  10 # without limitation, that your use is for the sole purpose of
  11 # programming logic devices manufactured by Altera and sold by
  12 # Altera or its authorized distributors.  Please refer to the
  13 # applicable agreement for further details.
  14
  15 # Quartus II: Generate Tcl File for Project
  16 # File: dt.tcl
  17 # Generated on: Mon Dec 20 12:10:32 2010
  18
  19 # Load Quartus II Tcl Project package
  20 package require ::quartus::project
  21
  22 set need_to_close_project 0
  23 set make_assignments 1
  24
  25 # Check that the right project is open
  26 if {[is_project_open]} {
  27         if {[string compare $quartus(project) "dt"]} {
  28                 puts "Project dt is not open"
  29                 set make_assignments 0
  30         }
  31 } else {
  32         # Only open if not already open
  33         if {[project_exists dt]} {
  34                 project_open -revision dt dt
  35         } else {
  36                 project_new -revision dt dt
  37         }
  38         set need_to_close_project 1
  39 }
  40
  41 # Make assignments
  42 if {$make_assignments} {
  43         set_global_assignment -name FAMILY Cyclone
  44         set_global_assignment -name DEVICE EP1C12Q240C8
  45         set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
  46         set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54  DECEMBER 16, 2010"
  47         set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
  48         set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
  49         set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
  50         set_global_assignment -name GENERATE_RBF_FILE ON
  51         set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
  52         set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
  53         set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
  54         set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
  55         set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
  56         set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
  57         set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
  58         set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
  59         set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
  60         set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
  61         set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
  62         set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
  63         set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
  64         set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
  65         set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
  66         set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd
  67         set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd
  68         set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
  69         set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
  70         set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
  71         set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
  72         set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
  73         set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
  74         set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
  75         set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
  76         set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
  77         set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
  78         set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
  79         set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
  80         set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
  81         set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
  82         set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
  83         set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
  84         set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
  85         set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
  86         set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
  87         set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
  88         set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
  89         set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
  90         set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
  91         set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
  92         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
  93         set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
  94         set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
  95         set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
  96         set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
  97         set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
  98         set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
  99         set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
 100         set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
 101         set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
 102         set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
 103         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
 104         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
 105         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
 106         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
 107         set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
 108         set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
 109         set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
 110         set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
 111         set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
 112         set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 113         set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
 114         set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 115         set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 116         set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
 117         set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
 118         set_location_assignment PIN_152 -to sys_clk
 119         set_location_assignment PIN_42 -to sys_res
 120         set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 121
 122         # Commit assignments
 123         export_assignments
 124
 125         # Close project
 126         if {$need_to_close_project} {
 127                 project_close
 128         }
 129 }