2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
11 use work.extension_7seg_pkg.all;
13 architecture behav of writeback_stage is
15 signal data_ram_read, data_ram_read_ext : word_t;
16 signal data_addr : word_t;
18 signal wb_reg, wb_reg_nxt : writeback_rec;
20 signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec;
22 signal sel_nxt, dmem_we, bus_rx :std_logic;
37 data_addr(DATA_ADDR_WIDTH+1 downto 2),
38 data_addr(DATA_ADDR_WIDTH+1 downto 2),
71 syn: process(clk, reset)
75 if (reset = RESET_VALUE) then
76 wb_reg.address <= (others => '0');
77 wb_reg.dmem_en <= '0';
78 wb_reg.dmem_write_en <= '0';
82 elsif rising_edge(clk) then
89 -- type writeback_rec is record
90 -- address : in word_t; --ureg
91 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
92 -- dmem_write_en : in std_logic; --ureg
93 -- hword_hl : in std_logic --ureg
98 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
101 wb_reg_nxt.address <= address;
102 wb_reg_nxt.dmem_en <= dmem_en;
103 wb_reg_nxt.dmem_write_en <= dmem_write_en;
104 wb_reg_nxt.hword <= hword;
105 wb_reg_nxt.byte_s <= byte_s;
107 regfile_val <= result; --(others => '0');
109 if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
110 regfile_val <= data_ram_read;
111 if (wb_reg.hword = '1') then
112 regfile_val <= (others => '0');
113 if (wb_reg.address(1) = '1') then
114 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
116 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
119 if (wb_reg.byte_s = '1') then
120 regfile_val <= (others => '0');
121 case wb_reg.address(1 downto 0) is
122 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
123 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
124 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
125 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
131 --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
132 jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
134 if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
135 jump_addr <= data_ram_read;
140 -- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
144 -- if ((alu_jmp and wb_reg.dmem_en) = '1') then
145 -- jump_addr <= data_ram_read;
150 -- result : in gp_register_t; --reg (alu result or jumpaddr)
151 -- result_addr : in gp_addr_t; --reg
152 -- address : in word_t; --ureg
153 -- alu_jmp : in std_logic; --reg
154 -- br_pred : in std_logic; --reg
155 -- write_en : in std_logic; --reg (register file)
156 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
157 -- dmem_write_en : in std_logic; --ureg
158 -- hword : in std_logic --ureg
162 out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
165 reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
166 reg_addr <= result_addr;
168 data_addr <= (others => '0');
171 if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
172 data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
173 dmem_we <= wb_reg_nxt.dmem_write_en;
178 addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
182 ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
183 ext_uart.byte_en <= (others => '0');
184 ext_uart.data <= (others => '0');
185 ext_uart.addr <= (others => '0');
188 ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
189 ext_7seg.byte_en <= (others => '0');
190 ext_7seg.data <= (others => '0');
191 ext_7seg.addr <= (others => '0');
194 ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
195 ext_timer.byte_en <= (others => '0');
196 ext_timer.data <= (others => '0');
197 ext_timer.addr <= (others => '0');
200 ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
201 ext_gpmp.byte_en <= (others => '0');
202 ext_gpmp.data <= (others => '0');
203 ext_gpmp.addr <= (others => '0');
204 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
205 case wb_reg_nxt.address(31 downto 4) is
206 when EXT_UART_ADDR =>
208 ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
209 ext_uart.data <= ram_data;
210 ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
211 case wb_reg_nxt.address(1 downto 0) is
212 when "00" => ext_uart.byte_en <= "0001";
213 when "01" => ext_uart.byte_en <= "0010";
214 when "10" => ext_uart.byte_en <= "0100";
215 --when "11" => ext_uart.byte_en <= "1000";
216 when "11" => ext_uart.byte_en <= "1111";
220 when EXT_7SEG_ADDR =>
222 ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
223 ext_7seg.data <= ram_data;
224 ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
225 ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
228 -- case wb_reg_nxt.address(1 downto 0) is
229 -- when "00" => ext_7seg.byte_en <= "0001";
230 -- when "01" => ext_7seg.byte_en <= "0010";
231 -- when "10" => ext_7seg.byte_en <= "0100";
232 -- when "11" => ext_7seg.byte_en <= "1000";
233 -- when others => null;
236 when EXT_TIMER_ADDR =>
238 ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
239 ext_timer.data <= ram_data;
240 ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
241 case wb_reg.address(1 downto 0) is
242 when "00" => ext_timer.byte_en <= "0001";
243 when "01" => ext_timer.byte_en <= "0010";
244 when "10" => ext_timer.byte_en <= "0100";
245 when "11" => ext_timer.byte_en <= "1000";
248 when EXT_GPMP_ADDR =>
250 ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
251 ext_gpmp.data <= ram_data;
252 ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
253 case wb_reg.address(1 downto 0) is
254 when "00" => ext_gpmp.byte_en <= "0001";
255 when "01" => ext_gpmp.byte_en <= "0010";
256 when "10" => ext_gpmp.byte_en <= "0100";
257 when "11" => ext_gpmp.byte_en <= "1000";
260 -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert