cpu/src/writeback_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6
   7 architecture behav of writeback_stage is
   8
   9
  10 begin
  11
  12 signal data_ram_read : word_t;
  13
  14 signal wb_reg, wb_reg_nxt : writeback_rec;
  15
  16         data_ram : r_w_ram
  17                 generic map (
  18                         PHYS_DATA_ADDR_WIDTH,
  19                         WORD_WIDTH
  20                 )
  21
  22                 port map (
  23                         clk,
  24                         wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
  25                         wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
  26                         wb_reg_nxt.dmem_write_en,
  27                         ram_data,
  28                         data_ram_read
  29                 );
  30
  31
  32 syn: process(sys_clk, reset)
  33
  34 begin
  35
  36         if (reset = RESET_VALUE) then
  37
  38         elsif rising_edge(sys_clk) then
  39                 wb_reg <= wb_reg_nxt;
  40         end if;
  41
  42 end process;
  43
  44 --      type writeback_rec is record
  45 --              address : in word_t;            --ureg
  46 --              dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
  47 --              dmem_write_en : in std_logic;   --ureg
  48 --              hword_hl : in std_logic         --ureg
  49 --      end record;
  50
  51
  52
  53 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)
  54
  55 begin
  56         wb_reg_nxt.address <= address;
  57         wb_reg_nxt.dmem_en <= dmem_en;
  58         wb_reg_nxt.dmem_write_en <= dmem_write_en;
  59         wb_reg_nxt.hword <= hword;
  60         wb_reg_nxt.byte_s <= byte_s;
  61
  62         regfile_val <= result; --(others => '0');
  63
  64         if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then   -- ram read operation --alu_jmp = '0' and
  65                 regfile_val <= data_ram_read;
  66                 if (wb_reg.hword = '1') then
  67                         regfile_val <= (others => '0');
  68                         if (wb_reg.address(1) = '1') then
  69                                 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
  70                         else
  71                                 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
  72                         end if;
  73                 end if;
  74                 if (wb_reg.byte_s = '1') then
  75                         regfile_val <= (others => '0');
  76                         case wb_reg.address(1 downto 0) is
  77                                 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
  78                                 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
  79                                 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
  80                                 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
  81                         end case;
  82                 end if;
  83         end if;
  84
  85         jump <= alu_jmp xor br_pred;
  86         jump_addr <= result;
  87         if ((alu_jmp and wb_reg.dmem_en) = '1') then
  88                 jump_addr <= data_ram_read;
  89         end if;
  90
  91 end process;
  92
  93 --                      result : in gp_register_t;      --reg  (alu result or jumpaddr)
  94 --                      result_addr : in gp_addr_t;     --reg
  95 --                      address : in word_t;            --ureg
  96 --                      alu_jmp : in std_logic;         --reg
  97 --                      br_pred : in std_logic;         --reg
  98 --                      write_en : in std_logic;        --reg  (register file)
  99 --                      dmem_en : in std_logic;         --ureg (jump addr in mem or in result)
 100 --                      dmem_write_en : in std_logic;   --ureg
 101 --                      hword : in std_logic            --ureg
 102
 103
 104
 105 out_logic: process(write_en, result_addr)
 106
 107 begin
 108         reg_we <= write_en;
 109         reg_addr <= result_addr;
 110 end process;
 111
 112 end behav;
 113