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4e5fba30c1e08b90d552e1f0b1e43ad19c54d1f4
[calu.git]
/
cpu
/
src
/
writeback_stage_b.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.core_pkg.all;
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architecture behav of writeback_stage is
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begin
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syn: process(sys_clk, reset)
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begin
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if (reset = RESET_VALUE) then
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elsif rising_edge(sys_clk) then
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end if;
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end process;
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end behav;
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