2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
11 use work.extension_7seg_pkg.all;
13 architecture behav of writeback_stage is
15 signal data_ram_read, data_ram_read_ext : word_t;
16 signal data_addr : word_t;
18 signal wb_reg, wb_reg_nxt : writeback_rec;
20 signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec;
21 signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
23 signal sel_nxt, dmem_we, ext_anysel : std_logic;
25 signal calc_mem_res : gp_register_t;
29 ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
30 ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
40 data_addr(DATA_ADDR_WIDTH+1 downto 2),
41 data_addr(DATA_ADDR_WIDTH+1 downto 2),
74 syn: process(clk, reset)
78 if (reset = RESET_VALUE) then
79 wb_reg.address <= (others => '0');
80 wb_reg.dmem_en <= '0';
81 wb_reg.dmem_write_en <= '0';
85 wb_reg.byte_en <= (others => '0');
86 wb_reg.data <= (others =>'0');
87 elsif rising_edge(clk) then
93 -- type writeback_rec is record
94 -- address : in word_t; --ureg
95 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
96 -- dmem_write_en : in std_logic; --ureg
97 -- hword_hl : in std_logic --ureg
102 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data)
103 variable byte_en : byte_en_t;
104 variable address_val : std_logic_vector(1 downto 0);
106 wb_reg_nxt.address <= address;
107 wb_reg_nxt.dmem_en <= dmem_en;
108 wb_reg_nxt.dmem_write_en <= dmem_write_en;
109 wb_reg_nxt.hword <= hword;
110 wb_reg_nxt.byte_s <= byte_s;
112 calc_mem_res <= result; --(others => '0');
114 wb_reg_nxt.data <= ram_data;
115 byte_en := (others => '0');
116 address_val := address(BYTEADDR-1 downto 0);
117 if dmem_en = '1' then
119 -- case address(BYTEADDR-1 downto 0) is
121 when "00" => byte_en(1 downto 0) := "11";
122 when "10" => byte_en(3 downto 2) := "11";
125 elsif byte_s = '1' then
126 -- case address(BYTEADDR-1 downto 0) is
128 when "00" => byte_en(0) := '1';
129 when "01" => byte_en(1) := '1';
130 when "10" => byte_en(2) := '1';
131 when "11" => byte_en(3) := '1';
135 byte_en := (others => '1');
138 wb_reg_nxt.byte_en <= byte_en;
140 -- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
141 -- calc_mem_res <= data_ram_read;
142 -- if (wb_reg.hword = '1') then
143 -- calc_mem_res <= (others => '0');
144 -- if (wb_reg.address(1) = '1') then
145 -- calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
147 -- calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
150 -- if (wb_reg.byte_s = '1') then
151 -- calc_mem_res <= (others => '0');
152 -- case wb_reg.address(1 downto 0) is
153 -- when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
154 -- when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
155 -- when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
156 -- when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
157 -- when others => null;
162 --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
163 jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
165 if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
166 jump_addr <= data_ram_read;
171 -- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
175 -- if ((alu_jmp and wb_reg.dmem_en) = '1') then
176 -- jump_addr <= data_ram_read;
181 -- result : in gp_register_t; --reg (alu result or jumpaddr)
182 -- result_addr : in gp_addr_t; --reg
183 -- address : in word_t; --ureg
184 -- alu_jmp : in std_logic; --reg
185 -- br_pred : in std_logic; --reg
186 -- write_en : in std_logic; --reg (register file)
187 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
188 -- dmem_write_en : in std_logic; --ureg
189 -- hword : in std_logic --ureg
193 out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s)
194 variable reg_we_v : std_logic;
195 variable data_out : gp_register_t;
197 reg_we_v := (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
198 reg_addr <= result_addr;
200 data_addr <= (others => '0');
203 if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
204 data_out := data_ram_read;
206 reg_we_v := reg_we_v and ext_anysel;
207 data_out := data_ram_read_ext;
210 if wb_reg.byte_en(0) = '0' then
211 data_out(byte_t'range) := (others => '0');
213 if wb_reg.byte_en(1) = '0' then
214 data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
216 if wb_reg.byte_en(2) = '0' then
217 data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
219 if wb_reg.byte_en(3) = '0' then
220 data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
224 -- if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
225 -- if wb_reg.address(1)='1' then
226 -- data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
228 -- data_out(data_out'high downto (data_out'length/2)) := (others => '0');
229 -- if byte_s = '1' then
230 -- if wb_reg.address(0) = '1' then
231 -- data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
233 -- data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
238 data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
240 if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
241 data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
242 dmem_we <= wb_reg_nxt.dmem_write_en;
245 regfile_val <= data_out;
247 if wb_reg.dmem_en = '0' then
248 regfile_val <= result;
256 addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
257 variable wr_en, enable : std_logic; -- these are all registered
258 variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
259 variable addr : ext_addr_t; -- for example the data memory, because it already has input registers
260 variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t;
261 variable data : gp_register_t;
264 --if selecting enable is too slow, see alu_b
265 enable := wb_reg.dmem_en;
266 wr_en := wb_reg.dmem_write_en;
267 byte_en := wb_reg.byte_en;
268 addr := wb_reg.address(gp_register_t'high downto BYTEADDR);
269 addrid := wb_reg.address(gp_register_t'high downto EXTWORDS);
277 ext_uart.wr_en <= wr_en;
278 ext_7seg.wr_en <= wr_en;
279 ext_timer.wr_en <= wr_en;
280 ext_gpmp.wr_en <= wr_en;
282 ext_uart.byte_en <= byte_en;
283 ext_7seg.byte_en <= byte_en;
284 ext_timer.byte_en <= byte_en;
285 ext_gpmp.byte_en <= byte_en;
287 ext_uart.addr <= addr;
288 ext_7seg.addr <= addr;
289 ext_timer.addr <= addr;
290 ext_gpmp.addr <= addr;
292 ext_uart.data <= data;
293 ext_7seg.data <= data;
294 ext_timer.data <= data;
295 ext_gpmp.data <= data;
296 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
298 when EXT_UART_ADDR =>
299 ext_uart.sel <= enable;
300 ext_anysel <= enable;
302 -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
303 -- ext_uart.data <= ram_data;
304 -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
305 -- case wb_reg_nxt.address(1 downto 0) is
306 -- when "00" => ext_uart.byte_en <= "0001";
307 -- when "01" => ext_uart.byte_en <= "0010";
308 -- when "10" => ext_uart.byte_en <= "0100";
309 -- --when "11" => ext_uart.byte_en <= "1000";
310 -- when "11" => ext_uart.byte_en <= "1111";
311 -- when others => null;
314 when EXT_7SEG_ADDR =>
315 ext_7seg.sel <= enable;
316 ext_anysel <= enable;
318 -- ext_7seg.wr_en <= wb_regdmem_write_en;
319 -- ext_7seg.data <= ram_data;
320 -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
321 -- ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
324 -- case wb_reg_nxt.address(1 downto 0) is
325 -- when "00" => ext_7seg.byte_en <= "0001";
326 -- when "01" => ext_7seg.byte_en <= "0010";
327 -- when "10" => ext_7seg.byte_en <= "0100";
328 -- when "11" => ext_7seg.byte_en <= "1000";
329 -- when others => null;
332 when EXT_TIMER_ADDR =>
333 ext_timer.sel <= enable;
334 ext_anysel <= enable;
335 -- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
336 -- ext_timer.data <= ram_data;
337 -- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
338 -- case wb_reg.address(1 downto 0) is
339 -- when "00" => ext_timer.byte_en <= "0001";
340 -- when "01" => ext_timer.byte_en <= "0010";
341 -- when "10" => ext_timer.byte_en <= "0100";
342 -- when "11" => ext_timer.byte_en <= "1000";
343 -- when others => null;
345 when EXT_GPMP_ADDR =>
346 ext_gpmp.sel <= enable;
347 ext_anysel <= enable;
348 -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
349 -- ext_gpmp.data <= ram_data;
350 -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
351 -- case wb_reg.address(1 downto 0) is
352 -- when "00" => ext_gpmp.byte_en <= "0001";
353 -- when "01" => ext_gpmp.byte_en <= "0010";
354 -- when "10" => ext_gpmp.byte_en <= "0100";
355 -- when "11" => ext_gpmp.byte_en <= "1000";
356 -- when others => null;
358 -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert
359 when others => ext_anysel <= '0';
362 data_ram_read_ext <= ext_uart_out or ext_gpmp_out or ext_timer_out;