cpu/src/writeback_stage_b.vhd.bak

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10
  11 architecture behav of writeback_stage is
  12
  13 signal data_ram_read : word_t;
  14
  15 signal wb_reg, wb_reg_nxt : writeback_rec;
  16 signal ext_uart :  extmod_rec;
  17
  18
  19
  20 begin
  21
  22
  23         data_ram : r_w_ram
  24                 generic map (
  25                         DATA_ADDR_WIDTH,
  26                         WORD_WIDTH
  27                 )
  28
  29                 port map (
  30                         clk,
  31                         wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
  32                         wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
  33                         wb_reg_nxt.dmem_write_en,
  34                         ram_data,
  35                         data_ram_read
  36                 );
  37
  38
  39 syn: process(clk, reset)
  40
  41 begin
  42
  43         if (reset = RESET_VALUE) then
  44                 wb_reg.address <= (others => '0');
  45                 wb_reg.dmem_en <= '0';
  46                 wb_reg.dmem_write_en <= '0';
  47                 wb_reg.hword <= '0';
  48                 wb_reg.byte_s <= '0';
  49         elsif rising_edge(clk) then
  50                 wb_reg <= wb_reg_nxt;
  51         end if;
  52
  53 end process;
  54
  55 --      type writeback_rec is record
  56 --              address : in word_t;            --ureg
  57 --              dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
  58 --              dmem_write_en : in std_logic;   --ureg
  59 --              hword_hl : in std_logic         --ureg
  60 --      end record;
  61
  62
  63
  64 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
  65
  66 begin
  67         wb_reg_nxt.address <= address;
  68         wb_reg_nxt.dmem_en <= dmem_en;
  69         wb_reg_nxt.dmem_write_en <= dmem_write_en;
  70         wb_reg_nxt.hword <= hword;
  71         wb_reg_nxt.byte_s <= byte_s;
  72
  73         regfile_val <= result; --(others => '0');
  74
  75         if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then   -- ram read operation --alu_jmp = '0' and
  76                 regfile_val <= data_ram_read;
  77                 if (wb_reg.hword = '1') then
  78                         regfile_val <= (others => '0');
  79                         if (wb_reg.address(1) = '1') then
  80                                 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
  81                         else
  82                                 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
  83                         end if;
  84                 end if;
  85                 if (wb_reg.byte_s = '1') then
  86                         regfile_val <= (others => '0');
  87                         case wb_reg.address(1 downto 0) is
  88                                 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
  89                                 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
  90                                 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
  91                                 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
  92                                 when others => null;
  93                         end case;
  94                 end if;
  95         end if;
  96
  97         jump <= alu_jmp xor br_pred;
  98         jump_addr <= result;
  99         if ((alu_jmp and wb_reg.dmem_en) = '1') then
 100                 jump_addr <= data_ram_read;
 101         end if;
 102
 103 end process;
 104
 105 --                      result : in gp_register_t;      --reg  (alu result or jumpaddr)
 106 --                      result_addr : in gp_addr_t;     --reg
 107 --                      address : in word_t;            --ureg
 108 --                      alu_jmp : in std_logic;         --reg
 109 --                      br_pred : in std_logic;         --reg
 110 --                      write_en : in std_logic;        --reg  (register file)
 111 --                      dmem_en : in std_logic;         --ureg (jump addr in mem or in result)
 112 --                      dmem_write_en : in std_logic;   --ureg
 113 --                      hword : in std_logic            --ureg
 114
 115
 116
 117 out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
 118
 119 begin
 120         reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
 121         reg_addr <= result_addr;
 122 end process;
 123
 124
 125 addr_de_mult: process(address)
 126
 127 begin
 128
 129   ext_uart.sel <='0';
 130   ext_uart.wr_en <= '0';
 131   ext_uart.byte_en <= (others => '0');
 132   ext_uart.data <= (others => '0');
 133   ext_uart.addr <= (others => '0');
 134  case wb_reg_nxt.address(wb_reg_nxt.address'high downto EXTWORDS) is
 135         when EXT_UART_ADDR =>
 136                 ext_uart.sel <='1';
 137                 ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 138                 ext_uart.data <= ram_data;
 139                 ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
 140                 case wb_reg.address(1 downto 0) is
 141                                 when "00" => ext_uart.byte_en <= "0001";
 142                                 when "01" => ext_uart.byte_en <= "0010";
 143                                 when "10" => ext_uart.byte_en <= "0100";
 144                                 when "11" => ext_uart.byte_en <= "1000";
 145                                 when others => null;
 146                         end case;
 147
 148
 149
 150         when others => null;
 151  end case;s
 152
 153 end process;
 154
 155 end behav;
 156