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965f996a0a8aa00d21e3824f5e11d3a5e1b1239b
[calu.git]
/
cpu
/
src
/
writeback_stage.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity writeback_stage is
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generic (
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-- active reset value
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RESET_VALUE : std_logic;
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-- active logic value
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LOGIC_ACT : std_logic;
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);
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port(
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--System inputs
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clk : in std_logic;
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reset : in std_logic;
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);
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end writeback_stage;