cpu/src/rw_r_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 architecture behaviour of rw_r_ram is
   7
   8         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
   9         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  10
  11         signal ram : RAM_TYPE; --:= (others=> x"00");
  12
  13 begin
  14         process(clk)
  15         begin
  16                 if rising_edge(clk) then
  17                         if wr_en = '1' then
  18                                 ram(to_integer(UNSIGNED(rw_addr))) <= data_in;
  19                                 rw_out <= data_in;
  20                         else
  21                                 rw_out <= ram(to_integer(UNSIGNED(rw_addr)));
  22                         end if;
  23                                 rd_out <= ram(to_integer(UNSIGNED(rd_addr)));
  24                 end if;
  25         end process;
  26 end architecture behaviour;