cpu/src/rw_r_ram.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 entity rw_r_ram is
   6         generic (
   7                                 ADDR_WIDTH : integer range 1 to integer'high;
   8                                 DATA_WIDTH : integer range 1 to integer'high
   9                         );
  10         port(
  11                 --System inputs
  12                         clk : in std_logic;
  13                 --Input
  14                         rw_addr, rd_addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
  15
  16                         wr_en : in std_logic;
  17                         data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
  18
  19                 --Output
  20                         rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
  21                 );
  22
  23 end entity rw_r_ram;