cpu/src/rom_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of rom is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal rrrr_addr : std_logic_vector(31 downto 0);
  16
  17         signal ram : RAM_TYPE := (
  18
  19
  20
  21                                   others => x"F0000000");
  22
  23 begin
  24         process(clk)
  25         begin
  26                 if rising_edge(clk) then
  27 --               data_out <= ram(to_integer(UNSIGNED(rd_addr)));
  28
  29
  30         case rrrr_addr(10 downto 0) is
  31
  32                                 when "00000000000" => data_out <= "11101101000000000000000000000000"; --
  33                                 when "00000000001" => data_out <= "11101101001000000000000000000000"; --
  34                                 when "00000000010" => data_out <= "11100111101000000000000000000000"; --
  35
  36                                 when "00000000011" => data_out <= "11100001000000000000000000100001"; --
  37                                 when "00000000100" => data_out <= "11101100100000000000001100000000"; --
  38                                 when "00000000101" => data_out <= "00001011011111111111111010000011"; --
  39
  40                                 when "00000000110" => data_out <= "11101101000000000000000000001000"; --
  41                                 when "00000000111" => data_out <= "11100111100000000000000000001111"; --
  42                                 when "00000001000" => data_out <= "11100111100000000000000000010011"; -- --
  43
  44
  45                                 when "00000001001" => data_out <= x"ed080080"; --x"ed080048"; --
  46                                 when "00000001010" => data_out <= x"ed500080"; --
  47                                 when "00000001011" => data_out <= x"fd500002"; --
  48                                 when "00000001100" => data_out <= x"eb000107";
  49                                 when "00000001101" => data_out <= "11101011000000000000011010000010"; --"11101011000000000000000000000010";
  50
  51                                 when "00000001110" => data_out <= x"e5088800";
  52                                 when "00000001111" => data_out <= x"e0150800";
  53                                 when "00000010000" => data_out <= x"e7010000";
  54                                 when "00000010001" => data_out <= x"ec800000";
  55                                 when "00000010010" => data_out <= x"0b000008";
  56                                 when "00000010011" => data_out <= x"e1910020";
  57                                 when "00000010100" => data_out <= x"eb7ffe07";
  58                                 when "00000010101" => data_out <= x"e7197ffc";
  59                                 when "00000010110" => data_out <= x"e0018000";
  60
  61                                 when "00000010111" => data_out <= x"e1110020";
  62                                 when "00000011000" => data_out <= x"e7810000";
  63                                 when "00000011001" => data_out <= x"eb00000a";
  64
  65
  66                                 when "00000011010" => data_out <= x"ed290080";
  67                                 when "00000011011" => data_out <= x"e1080000";
  68
  69                                 when "00000011100" => data_out <= x"e78a8000";
  70
  71                                 when others => data_out <= "11101011000000000000000000000010";
  72
  73                         end case;
  74
  75                         if wr_en = '1' then
  76                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  77                         end if;
  78                 end if;
  79         end process;
  80
  81         rrrr_addr(10 downto 0) <= rd_addr;
  82         rrrr_addr(31 downto 11) <= (others => '0');
  83 end architecture behaviour;