3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
9 architecture behaviour of ram_xilinx is
10 type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
11 subtype stfu_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
12 type ram_t is array (0 to (2**ADDR_WIDTH)-1) of stfu_t;
13 signal ram0 : ram_t := (others => x"00");
14 signal ram1 : ram_t := (others => x"00");
15 signal ram2 : ram_t := (others => x"00");
16 signal ram3 : ram_t := (others => x"00");
17 signal q_local : word_t;
19 begin -- Re-organize the read data from the RAM to match the output
20 unpack: for i in 0 to 3 generate
21 q(8*(i+1) - 1 downto 8*i) <= q_local(i);
26 if(rising_edge(clk)) then
29 ram0(to_integer(UNSIGNED(waddr))) <= wdata(7 downto 0);
32 ram1(to_integer(UNSIGNED(waddr))) <= wdata(15 downto 8);
35 ram2(to_integer(UNSIGNED(waddr))) <= wdata(23 downto 16);
38 ram3(to_integer(UNSIGNED(waddr))) <= wdata(31 downto 24);
41 q_local(0) <= ram0(to_integer(UNSIGNED(raddr)));
42 q_local(1) <= ram1(to_integer(UNSIGNED(raddr)));
43 q_local(2) <= ram2(to_integer(UNSIGNED(raddr)));
44 q_local(3) <= ram3(to_integer(UNSIGNED(raddr)));
48 end architecture behaviour;