cpu/src/r_w_ram_be_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram_be is
   9
  10         type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
  11         type ram_t is array (0 to (2**ADDR_WIDTH)-1) of word_t;
  12         signal ram : ram_t := (others => ((x"00"), (x"00"), (x"00"), (x"00")));
  13         signal q_local : word_t;
  14
  15 begin -- Re-organize the read data from the RAM to match the output
  16         unpack: for i in 0 to 3 generate
  17                 q(8*(i+1) - 1 downto 8*i) <= q_local(i);
  18         end generate unpack;
  19
  20         process(clk)
  21         begin
  22                 if(rising_edge(clk)) then
  23                         if(we = '1') then
  24                                 if(be(0) = '1') then
  25                                         ram(to_integer(UNSIGNED(waddr)))(0) <= wdata(7 downto 0);
  26                                 end if;
  27                                 if be(1) = '1' then
  28                                         ram(to_integer(UNSIGNED(waddr)))(1) <= wdata(15 downto 8);
  29                                 end if;
  30                                 if be(2) = '1' then
  31                                         ram(to_integer(UNSIGNED(waddr)))(2) <= wdata(23 downto 16);
  32                                 end if;
  33                                 if be(3) = '1' then
  34                                         ram(to_integer(UNSIGNED(waddr)))(3) <= wdata(31 downto 24);
  35                                 end if;
  36                         end if;
  37                         q_local <= ram(to_integer(UNSIGNED(raddr)));
  38                 end if;
  39         end process;
  40
  41 end architecture behaviour;