cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal ram : RAM_TYPE := (
  16 0 => x"ed080048",       --;ldi r1, 9;;
  17 1 => x"ed500080",       --;ldil r10, list@lo ;; global pointer
  18 2 => x"fd500002",       --;ldih r10, list@hi;;
  19 3 => x"eb000107",       --;call+ fibcall;;
  20 4 => x"eb7ffe03",       --;br+ main;;
  21                 --2; fib(n) {
  22                 --2;   if (list[n] > 0) {
  23                 --2;    return list[n]
  24                 --2;   }
  25                 --2;   a = fib(n-1)
  26                 --2;   list[n] = a + list[n-2]
  27                 --2;   return list[n]
  28                 --2; }
  29                 --3;fibcall;
  30                 --2;update counter for aligned access
  31 5 => x"e5088800",       --;lls r1, r1, 2 ;; *4
  32                 --2;calculate adress of top element
  33 6 => x"e0150800",       --;add r2, r10, r1;;
  34                 --3;fibmem;
  35                 --2;load top element
  36 7 => x"e7010000",       --;ldw r0, 0(r2);;
  37                 --2;compare if set
  38 8 => x"ec800000",       --;cmpi r0, 0;;
  39                 --2;return if set
  40 9 => x"0b000008",       --;retnz-;;
  41                 --2;decrement adress for next lopp
  42 10 => x"e1910020",      --;subi r2, r2, 4;;
  43                 --2;iterative call for n-1 element
  44 11 => x"eb7ffe07",      --;call+ fibmem;;
  45                 --2;load n-2 element
  46 12 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
  47                 --2;add n-1 and n-2 element
  48 13 => x"e0018000",      --;add r0, r3, r0;;
  49                 --2;increment address for n element
  50                 --2;is needed because after return
  51                 --2;we need r2 to be set to the address
  52                 --2;of element n
  53 14 => x"e1110020",      --;addi r2, r2, 4;;
  54                 --2;store fib n
  55 15 => x"e7810000",      --;stw r0, 0(r2);;
  56 16 => x"eb00000a",      --;ret+;;
  57
  58
  59
  60
  61                                   others => x"F0000000");
  62
  63 --      signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
  64 --
  65 --                                  1 => "11101101000010000000000000111000", -- r1 = 7
  66 --                                  2 => "11101101000100000000000000101000", -- r2 = 5
  67 --                                  3 => "11101101000110000000000000100000", -- r3 = 4
  68 --                                  4 => "11100000001000010001100000000000", -- r4 = r2 + r3
  69 --                                  5 => "11100010001010100000100000000000", -- r5 = r4 and r1
  70 --
  71 --                                  6 => "11100001000000000000000000001000", -- r0 = r0 + 1
  72 --                                  7 => "11101100100000000000000000011000", -- cmpi r0 , 2
  73 --
  74 --                                  8 => "00001011011111111111110010000111", -- jump -7
  75 --                                  9 => "11101011000000000000000010000010", -- jump +1
  76 --                                 --10 => "11101011000000000000000010000010", -- jump +1
  77 --
  78   --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
  79         --                         11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
  80 --
  81 --                                 12 => "11101011000000000000000000000010", -- jump +0
  82
  83
  84
  85
  86 --                                others => x"F0000000");
  87
  88 --      signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  89 --                                  1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  90 --                                  2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  91 --                                  3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  92 --                                  4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  93 --                                  5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  94 --                                  6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
  95 --                                  7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
  96 --                                  8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
  97 --                                  9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
  98 --                                 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
  99 --                                 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
 100 --                                 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
 101 --                                 13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
 102 --                                 14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
 103 --                                 15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
 104 --                                 16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
 105 --                                 17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
 106 --                                 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
 107 --                                 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
 108 --                                others => x"F0000000");
 109
 110
 111 begin
 112         process(clk)
 113         begin
 114                 if rising_edge(clk) then
 115                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
 116
 117                         if wr_en = '1' then
 118                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
 119                         end if;
 120                 end if;
 121         end process;
 122 end architecture behaviour;