cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13         signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0
  14                                     1 => "11100000000110001000000000000000", --add r3, r1, r0
  15                                     2 => "11100000001000011001000000000000", --add r4, r3, r2
  16                                     3 => "11100000000100001000000000000000", --add r2, r1, r0
  17                                     4 => "11100000000110001000000000000000", --add r3, r1, r0
  18                                     5 => "11100000001000011001000000000000", --add r4, r3, r2
  19                                     6 => "11101100000000001000000000000000", --cmp r0 , r1
  20                                     7 => "00000000001010101010000000000001", --addnqd r5, r5, r4
  21                                     8 => "00000000001010101010000000000000", --addnq r5, r5, r4
  22                                     9 => "11101100001000100000000000000000", --cmp r4 , r4
  23                                    10 => "00000001001100001000000001010000", --addinq r5, r1, 10
  24                                    11 => "00010001001100001000000001010000", --addieq r5, r1, 10
  25                                    12 => "00010001101100110000000001010000", --subieq r5, r5, 10
  26                                    13 => "11100000000100001000000000000000", --add r2, r1, r0
  27                                    14 => "11100010000100001000000000000000", --and r2, r1, r0
  28                                    15 => "11101100000000001000000000000000", --cmp r0 , r1
  29                                    16 => "10000000001010101010000000000001", --addabd r5, r5, r4
  30                                    17 => "10110011101110001000010000110001", --orxltd r7, 1086
  31                                    18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1
  32                                    19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2
  33                                   others => x"F0000000");
  34
  35
  36 begin
  37         process(clk)
  38         begin
  39                 if rising_edge(clk) then
  40                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
  41
  42                         if wr_en = '1' then
  43                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  44                         end if;
  45                 end if;
  46         end process;
  47 end architecture behaviour;