cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal ram : RAM_TYPE := (
  16
  17         0 => "11101101000000000000000000000000",
  18         1 => "11101101001000000000000000000000",
  19         2 => "11100111101000000000000000000000",
  20         3 => "11100001000000000000000000100001",
  21         4 => "11101100100000000000010000000000",
  22         5 => "00001011011111111111111010000011",
  23
  24 6 => x"ed080048",       --;ldi r1, 9;;
  25 7 => x"ed500080",       --;ldil r10, list@lo ;; global pointer
  26 8 => x"fd500002",       --;ldih r10, list@hi;;
  27 9 => x"eb000107",       --;call+ fibcall;;
  28 10 => x"eb7ffe03",      --;br+ main;;
  29                 --2; fib(n) {
  30                 --2;   if (list[n] > 0) {
  31                 --2;    return list[n]
  32                 --2;   }
  33                 --2;   a = fib(n-1)
  34                 --2;   list[n] = a + list[n-2]
  35                 --2;   return list[n]
  36                 --2; }
  37                 --3;fibcall;
  38                 --2;update counter for aligned access
  39 11 => x"e5088800",      --;lls r1, r1, 2 ;; *4
  40                 --2;calculate adress of top element
  41 12 => x"e0150800",      --;add r2, r10, r1;;
  42                 --3;fibmem;
  43                 --2;load top element
  44 13 => x"e7010000",      --;ldw r0, 0(r2);;
  45                 --2;compare if set
  46 14 => x"ec800000",      --;cmpi r0, 0;;
  47                 --2;return if set
  48 15 => x"0b000008",      --;retnz-;;
  49                 --2;decrement adress for next lopp
  50 16 => x"e1910020",      --;subi r2, r2, 4;;
  51                 --2;iterative call for n-1 element
  52 17 => x"eb7ffe07",      --;call+ fibmem;;
  53                 --2;load n-2 element
  54 18 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
  55                 --2;add n-1 and n-2 element
  56 19 => x"e0018000",      --;add r0, r3, r0;;
  57                 --2;increment address for n element
  58                 --2;is needed because after return
  59                 --2;we need r2 to be set to the address
  60                 --2;of element n
  61 20 => x"e1110020",      --;addi r2, r2, 4;;
  62                 --2;store fib n
  63 21 => x"e7810000",      --;stw r0, 0(r2);;
  64 22 => x"eb00000a",      --;ret+;;
  65
  66
  67
  68
  69                                   others => x"F0000000");
  70
  71 --      signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
  72 --
  73 --                                  1 => "11101101000010000000000000111000", -- r1 = 7
  74 --                                  2 => "11101101000100000000000000101000", -- r2 = 5
  75 --                                  3 => "11101101000110000000000000100000", -- r3 = 4
  76 --                                  4 => "11100000001000010001100000000000", -- r4 = r2 + r3
  77 --                                  5 => "11100010001010100000100000000000", -- r5 = r4 and r1
  78 --
  79 --                                  6 => "11100001000000000000000000001000", -- r0 = r0 + 1
  80 --                                  7 => "11101100100000000000000000011000", -- cmpi r0 , 2
  81 --
  82 --                                  8 => "00001011011111111111110010000111", -- jump -7
  83 --                                  9 => "11101011000000000000000010000010", -- jump +1
  84 --                                 --10 => "11101011000000000000000010000010", -- jump +1
  85 --
  86   --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
  87         --                         11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
  88 --
  89 --                                 12 => "11101011000000000000000000000010", -- jump +0
  90
  91
  92
  93
  94 --                                others => x"F0000000");
  95
  96 --      signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  97 --                                  1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  98 --                                  2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  99 --                                  3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
 100 --                                  4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
 101 --                                  5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
 102 --                                  6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
 103 --                                  7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
 104 --                                  8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
 105 --                                  9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
 106 --                                 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
 107 --                                 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
 108 --                                 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
 109 --                                 13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
 110 --                                 14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
 111 --                                 15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
 112 --                                 16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
 113 --                                 17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
 114 --                                 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
 115 --                                 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
 116 --                                others => x"F0000000");
 117
 118
 119 begin
 120         process(clk)
 121         begin
 122                 if rising_edge(clk) then
 123                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
 124
 125                         if wr_en = '1' then
 126                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
 127                         end if;
 128                 end if;
 129         end process;
 130 end architecture behaviour;