3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r_w_ram is
10 subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
11 type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
13 -- r0 = 0, r1 = 1, r2 = 3, r3 = A
15 signal ram : RAM_TYPE := ( 0 => "11101101000000000000000000000000", -- r0 = 0
17 1 => "11101101000010000000000000111000", -- r1 = 7
18 2 => "11101101000100000000000000101000", -- r2 = 5
19 3 => "11101101000110000000000000100000", -- r3 = 4
20 4 => "11100000001000010001100000000000", -- r4 = r2 + r3
21 5 => "11100010001010100000100000000000", -- r5 = r4 and r1
23 6 => "11100001000000000000000000001000", -- r0 = r0 + 1
24 7 => "11101100100000000000000000011000", -- cmpi r0 , 2
26 8 => "00001011011111111111110010000011", -- jump -7
27 9 => "11101011000000000000000010000010", -- jump +1
28 --10 => "11101011000000000000000010000010", -- jump +1
30 10 => "11100111101010100000000000000001", -- stw r5,r4,1
31 11 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001
33 12 => "11101011000000000000000000000010", -- jump +0
38 others => x"F0000000");
40 -- signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
41 -- 1 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
42 -- 2 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
43 -- 3 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
44 -- 4 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
45 -- 5 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
46 -- 6 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
47 -- 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
48 -- 8 => "00000000001010101010000000000000", --addnq r5, r5, r4 => r5 = 4
49 -- 9 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
50 -- 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
51 -- 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
52 -- 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
53 -- 13 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
54 -- 14 => "11100010000100001000000000000000", --and r2, r1, r0 => r2 = 0
55 -- 15 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
56 -- 16 => "10000000001010101010000000000001", --addabd r5, r5, r4 => r5 = 6
57 -- 17 => "10110011101110001000010000110001", --orxltd r7, 1086 => r7 = 1086
58 -- 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
59 -- 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
60 -- others => x"F0000000");
66 if rising_edge(clk) then
67 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
70 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
74 end architecture behaviour;