cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal ram : RAM_TYPE := (  0 => "11101101000010000000000000111000", -- r1 = 7
  16                                     1 => "11101101000100000000000000101000", -- r2 = 5
  17                                     2 => "11101101000110000000000000100000", -- r3 = 4
  18                                     3 => "11100000001000010001100000000000", -- r4 = r2 + r3
  19                                     4 => "11100010001010100000100000000000", -- r5 = r4 and r1
  20                                     5 => "11100111101010100000000000000001", -- stw r5,r4,1
  21
  22                                   others => x"F0000000");
  23
  24 --      signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  25 --                                  1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  26 --                                  2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  27 --                                  3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
  28 --                                  4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
  29 --                                  5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
  30 --                                  6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
  31 --                                  7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
  32 --                                  8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
  33 --                                  9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
  34 --                                 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
  35 --                                 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
  36 --                                 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
  37 --                                 13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
  38 --                                 14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
  39 --                                 15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
  40 --                                 16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
  41 --                                 17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
  42 --                                 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
  43 --                                 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
  44 --                                others => x"F0000000");
  45
  46
  47 begin
  48         process(clk)
  49         begin
  50                 if rising_edge(clk) then
  51                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
  52
  53                         if wr_en = '1' then
  54                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  55                         end if;
  56                 end if;
  57         end process;
  58 end architecture behaviour;